• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.74-81
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• 2007

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 1GSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. further, a novel layout technique is introduced for compact area. With the clock speed of 1GSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 500MHz, while consuming only 60mW of power. The measured INL and DNL were within $\pm$0.5 LSB, $\pm$0.7 LSB, respectively. The measured SNR was 34.1dB, when the Fin=100MHz at Fs=300MHz. The active chip occupies an area of 0.27$mm^2$ in 0.18um CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.263-268
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• 2004

In this paper, we motivate the post-mask performance enhancement technique combined with the Multi-Threshold Voltage CMOS (MTCMOS) leakage current suppression technology, and integrate the new design issues related to the MTCMOS technology into the ASIC design methodology. The issues include short-circuit current and sneak leakage current prevention. Towards validating the proposed techniques, a Personal Digital Assistant (PDA) processor has been implemented using the methodology, and a 0.18um process. The fabricated PDA processor operates at 333MHz which has been improved about 23% at no additional cost of redesign and masks, and consumes about 2uW of standby mode leakage power which could have been three orders of magnitude larger if the MTCMOS technology was not applied.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.581-584
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• 2004

This paper presents an efficient heuristic algorithm to avoid crosstalk which effects to delay of CMOS digital circuit by downsizing and upsizing of Gate. The proposed algorithm divide into two step, step1 performs downsizing of gate, step2 performs upsizing, so that avoid adjacent aggressor to critical path in series. The proposed algorithm has been verified on LGSynth91 benchmark circuits and Experimental results show an average $8.64\%$ Crosstalk Avoidance effect. This result proved new potential of proposed algorithm.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.67-70
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• 2003

In this paper the main topologies of one-bit full adders, including the most interesting of those recently proposed, are analyzed and compared for speed, power consumption, and power-delay product. The comparison has been performed on circuits, optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a Cadence environment using a 0.25-${\mu}m$ process, also including the parasitics derived from layout. Performance has been also compared for different supply voltage values. Thus design guidelines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare n-bit adders implemented as a chain of one-bit full adders. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, except for short chains of blocks or for cases where minimum power consumption is desired, topologies with only pass transistors or transmission gates are not attractive.

• Journal of Electrical Engineering and Technology
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• v.3 no.3
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• pp.430-435
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• 2008

In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using $0.18{\mu}\;m$ CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.563-564
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• 2006

A single photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has been designed using $0.25{\mu}m$triple well CMOS process.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2016.11a
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• pp.129-130
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• 2016

본 논문에서는 다중 입력의 크기를 비교하기 위한 알고리즘 및 VLSI 구조를 제안한다. 제안하는 알고리즘은 여러 입력을 동시에 비교한 후에 간단한 디지털 논리 함수를 이용하여 그 입력들 중에서 가장 큰 값(혹은 가장 작은 값)을 검출하는 방법을 제공할 수 있다. 이 방식의 단점은 하드웨어 자원이 증가하는 것인데, 이를 위해 중복된 논리 연산을 재사용하는 방법도 제안한다. 제안하고자 하는 방식은 회로 속도의 증가, 즉 지연시간의 감소에 초점을 맞추었다. 제안한 비교 알고리즘은 HDL로 설계한 후에 Magna Chip의 $0.18{\mu}m$ CMOS 라이브러리를 이용하여 구현하였다. 제안한 비교방법은 전통적인 방식에 비해서 4 및 8 입력인 경우에 약 0.5 및 1.1배 만큼 하드웨어 자원을 더 소비하면서, 약 1.5 및 1.8배 만큼 동작 주파수를 향상시킬 수 있었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1008-1012
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• 2005

최근 디지털 카메라, 영상관련 디지털 기기들의 증가와 DMB(Digital Multimedia Broadcasting)의 시작으로 영상 처리 분야의 중요성이 점차 높아지고 있으며, 적절히 교정하지 못한 영상은 너무 밝거나 또는 너무 어둡게 보일 수 있기 때문에 영상을 컴퓨터 스크린에 정확하게 표현하는 감마교정은 영상을 디스플레이 하는 장치에서 더 많은 비중을 차지하고 있다. 본 논문에서는 영상 입력 장치 또는 카메라 이미지 센서로부터 얻은 Bayer Data 가 전처리 과정에서 수행하는 감마교정에 대해 이해하고, ROM에 감마 값을 고정하여 수행하지 않았다. 구간 선형 알고리즘을 이용한 하드웨어적인 처리를 수행하는 감마 교정을 구현하고자 한다. 이를 위해서 Visual C++을 이용하여 소프트웨어적인 구현과 구간 선형법 알고리즘을 이용한 구현을 검증한 후, 구간 선형 알고리즘을 적용한 감마 교정을 하드웨어로 설계 후, Modelsim6.0a를 이용하여 데이터를 검증한다.

• ETRI Journal
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• v.25 no.5
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• pp.337-344
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• 2003

In this paper, we introduce a fully synthesizable 32-bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35-${\mu}m$ library and a 0.18-${\mu}m$ library. With the 0.35-${\mu}m$ library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18-${\mu}m$ library.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.1-11
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• 1997

We developed a base station modulator ASIC for CDMA digital cellular system. In CDMA digital cellular system, the modulation is performed by convolutional encoding and QPSK with spread spectrum. The function blocks of base station modulator are CRC, convolutional encoder, interleaver pseudo-moise scrambler, power control bit puncturing, walsh cover, QPSK, gain controller, combiner and multiplexer. Each function block was designed by the logic synthesis of VHDL codes. The VHDL code was described at register transfer level and the size of code is about 8,000 lines. The circuit simulation and logic simulation were performed by COMPASS tools. The chip (ES-C2212B CMB) contains 25,205 gates and 3 Kbit SRAM, and its chip size is 5.25 mm * 5,45 mm in 0.8 mm CMOS cell-based design technology. It is packaged in 68 pin PLCC and the power dissipation at 10MHz is 300 mW at 5V. The ASIC has been fully tested and successfully working on the CDMA base station system.