• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.605-606
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• 2006

Voltage Controlled Oscillator(VCO) plays an important role in today's communication systems. Especially, a Clock Generator(CG) in phase-locked loop(PLL) is usually realized by the VCO. This paper proposes a new VCO with a controllable duty cycle buffer, that can be adopted in low-power high-speed communication systems. Delay cell of the VCO is implemented with gilbert cell. Frequency dynamic range of the VCO is in the range of approximately $50MHz{\sim}500MHz$. Parameters with N-well CMOS 0.18-um process with 1.8V supply voltage was used for the simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.50-50
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• 2001

IDDQ 테스트는 CMOS VLSI 회로에서 발생 가능한 여러 종류의 물리적 결함을 효율적으로 검출 할 수 있는 테스트 방식이다. 본 논문에서는 CMOS에서 발생 빈도가 가장 높은 합선고장을 효과적으로 검출할 수 있는 IDDQ 테스트 알고리즘을 이용하여 패턴 생성기를 개발하였다. 고려한 합선고장 모델은 회로의 레이아웃 정보에 의존하지 않으며, 내부노드 혹은 외부노드에 한정시킨 합선고장이 아닌 테스트 대상회로의 모든 노드에서 발생 가능한 단락이다. 구현된 테스트 패턴 생성기는 O(n2)의 복잡도를 갖는 합선고장과 전압 테스트 방식에 비해 상대적으로 느린 IDDQ 테스트를 위해서 새롭게 제안한 이웃 조사 알고리즘과 고장 collapsing 알고리즘을 이용하여, 빠른 고장 시뮬레이션 시간과 높은 고장 검출율을 유지하면서 적은 수의 테스트 패턴 생성이 가능하다. ISCAS 벤치마크 회로의 모의실험을 통하여 기존의 다른 방식보다 우수한 성능을 보였다.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.243-248
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• 2008

This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.292-301
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• 2001

IDDQ Testing is a very effective testing method to detect many kinds of physical defects occurred in CMOS VLSI circuits. In this paper, we consider the most commonly occurring bridging faults in current CMOS technologies and develop pattern generator for IDDQ testing using efficient IDDQ test algorithms. The complete set of bridging faults between every pair of all nodes(internal and external nodes) within circuit under test is assumed as target fault model. The merit of considering the complete bridging fault set is that layout information is not necessary. Implemented test pattern generator uses a new neighbor searching algorithm and fault collapsing schemes to achieve fast run time, high fault coverage, and compact test sets. Experimental results for ISCAS benchmark circuits demonstrate higher efficiency than those of previous methods.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.101-112
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• 2004

In this paper, we developed a numerical analysis model by using ADI-FDTD method to analyze three-dimensional interconnect structure. We discretized maxwell's curl equation by using ADI-FDTD. Using ADI-FDTD method, a sampler circuit designed from 3.3 V CMOS technology is simplified to 3-metal line structure. Using this simplified structure, the time delay and signal distortion of complex interconnects are investigated. As results of simulation, 5∼10 ps of delay time and 0.1∼0.2 V of signal distortion are measured. As demonstrated in this paper, the full-wave analysis using ADI-FDTD exhibits a promise for accurate modeling of electromagnetic phenomena in high-speed VLSI interconnect.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.47-53
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• 2004

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are composed with ternary voltage mode NMAX, NMIN, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.35um CMOS technology and 3.3Volts supply voltage. The architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.6
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• pp.564-571
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• 2001

This paper presents the VLSI design of highly efficient low voltage DC/DC converter for portable devices. All active devices are integrated on a single chip using a standard 0.65$\mu\textrm{m}$ CMOS process. The converter operates at the switching frequency of 1MHz for reducing the size of passive elements and uses a ZVS for minimizing the switching loss at high frequency. Simulation results show that the circuit can achieve a 95% efficiency when the output voltage is controlled to be 2V with the load of lW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.17-17
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• 2001

본 논문은 0.6㎛ CMOS 기술로 LZSS 알고리즘과 엔트로피 부호를 이용한 부호기/복호기 단일-칩의 본 논문은 0.6uul CMOS 기술로 LZSS 알고리즘과 엔트로피 부호를 이용한 부호기/복호기 단일-칩의 VLSI 설계 및 구현에 관하여 기술하였다. 처리 속도 50MHz를 갖는 사전탐색처리장치(DISP)의 메모리는 2K×Bbit 크기를 사용하였다. 이것은 매번 33개 클럭 중 한 개의 클럭은 사전의 WINDOW 배열을 갱신으로 사용하고 나머지 클럭은 주기마다 한 개의 데이터 기호를 바이트 단위로 압축을 실행한다. 결과적으로, LZSS 부호어 출력에 엔트로피 부호를 적용하여 46%의 평균 압축률을 보였다. 이것은 LZSS에 보다 7% 정도의 압축 성능이 향상된 것이다.