• Journal of electromagnetic engineering and science
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• v.9 no.1
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• pp.7-11
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• 2009

An Ultra-WideBand(UWB) Low-Noise Amplifier(LNA) is proposed and is implemented in a $0.18-{\mu}m$ CMOS technology. The proposed UWB LNA provides excellent wideband characteristics by combining a High-Pass Filter (HPF) with a conventional resistive-loaded LNA topology. In the proposed UWB LNA, the bell-shaped gain curve of the overall amplifier is much less dependent on the frequency response of the HPF embedded in the input stage. In addition, the adoption of fewer on-chip inductors in the input matching network permits a lower noise figure and a smaller chip area. Measurement results show a power gain of + 10 dB and an input return loss of more than - 9 dB over 2.7 to 6.2 GHz, a noise figure of 3.1 dB at 3.6 GHz and 7.8 dB at 6.2 GHz, an input PldB of - 12 dBm, and an IIP3 of - 0.2 dBm, while dissipating only 4.6 mA from a 1.8-V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.86-93
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• 2008

A low-power, low-noise, highly-linear hybrid balun circuit is proposed for 2.4-GHz fully differential CMOS direct conversion receivers. The hybrid balun is composed of a passive transformer and loss-compensating auxiliary amplifiers. Design issues regarding the optimal signal splitting and coupling between the transformer and compensating amplifiers are discussed. Implemented in $0.18{\mu}m$ CMOS process, the 2.4 GHz hybrid balun achieves 2.8 dB higher gain and 1.9 dB lower noise figure than its passive counterpart and +23 dBm of IIP3 only at a current consumption of 0.67 mA from 1.2 V supply. It is also examined that the hybrid balun can remarkably lower the total noise figure of a 2.4 GHz fully differential RF receiver only at a cost of 0.82 mW additional power dissipation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.65-71
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• 2010

This paper presents a 14-band LO generator architecture for MB-OFDM UWB systems using 3.1 GHz~10.6 GHz frequency band. The proposed LO generator architecture has been consisted of only one PLL and the fewest nonlinear components to generate 14 LO signals with high purity while consuming low dc power consumption. In addition, major spurious generated from the LO generator have been located in the out of UWB band. The proposed LO generator has been implemented in a $0.13-{\mu}m$ CMOS technology and consumes a dc power consumption of 93~103 mW from a 1.5 V supply. The simulation results show an in-band spurious suppression ratio of more than 41 dBc and a band-switching time of below 3 nsec.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.275-280
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• 2006

We propose Doherty power amplifier structure which can be integrated in Silicon RF ICs. Doherty power amplifiers are widely used in RF transmitters, because of their high Power Added Efficiency (PAE) and good linearity. In this paper, it is proposed that a method to replace the quarter wavelength coupler with IQ up-conversion mixers to achieve 90 degree phase shift, which allows on-chip Doherty amplifier. This idea is implemented and manufactured in CMOS 5 GHz band direct-conversion RF transmitter. We measured a 3dB improvement output RF power and linearity.