• 대한전자공학회논문지SD
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• 제47권2호
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• pp.100-105
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• 2010

본 논문에서는 Zero-Crossing 복조기에 적합한 88MHz에서 108MHz 대역 FM 라디오 수신기를 $0.5{\mu}m$ CMOS 공정을 이용하여 설계 및 제작하였다. 본 수신기는 Low-IF 구조를 기초로 설계되었으며, Low-Noise Amplifier (LNA), Down-Conversion Mixer, Phase locked loop (PLL), Low-pass filter (LPF), 비교기를 포함하는 RF/Analog 집적회로로 개발되었다. 측정결과 LNA와 Mixer를 포함하는 RF Block은 23.2dB의 변환 이득과 입력 PldB는 -14dBm였고 전체 잡음지수는 15 dB로 나타났다. IF단 LPF와 비교기를 포함하는 Analog Block은 89dB 이상의 전압 이득을 가지고, IC내부의 레지스터를 제어하여 600KHz에서 1.3MHz까지 100KHz 단위로 Passband 대역를 조절할 수 있도록 설계되었다. 설계된 수신기는 4.5V에서 동작하며, 전체 전류 소모는 15.3 mA로 68.85mW의 전력을 소모한다. 실험결과 성공적으로 FM 라디오 신호를 수신할 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 학술대회 논문집 정보 및 제어부문
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• pp.217-218
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• 2008

Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. A general method for achieving both reduced VCO gain(Kvco) and wide frequency band is to use the switched-capacitor bank LC VCO. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO with reduced variation of VCO gain and frequency steps. Buffers, divide-by-2 circuits and control logics the simulation results show that the designed circuit has a phase noise at 100kHz better than -106dBc/Hz throughout the signal band and consumes $9.5{\sim}13mA$ from a 1.8V supply.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.195-196
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• 2007

Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO, five divide-by-2 circuits and several buffers. The simulation results show that the designed circuit has a phase noise at 10kHz better than -87dBc/Hz throughout the signal band and consumes 10mA from a 1.8V supply.

• 전자공학회논문지
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• 제52권4호
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• pp.88-95
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• 2015

본 논문에서는 부성저항을 생성하는 회로로 알려진 RFNR 회로에 대한 새로운 분석을 소개한다. 새로운 분석에서는 RFNR 회로에 대한 수식분석의 정확성을 높이기 위해 트랜지스터의 게이트 저항과 소스 커패시턴스에 의한 영향을 고려하였다. 기존의 분석에서는 트랜지스터의 소스를 통하여 수식을 분석하였지만 제안된 수식에서는 회로의 공진부인 트랜지스터의 게이트를 통하여 회로를 분석했다. 그 결과, 제안하는 분석은 고주파수에서 기존의 분석보다 정확도를 향상시킬 수 있었다. 본 논문에서는 시뮬레이션을 통해 고주파수에서 분석의 정확도를 검증하였다.

• 전기학회논문지
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• 제57권5호
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• pp.889-895
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• 2008

In this paper a Fractional-N frequency synthesizer is designed for UHF RFID readers. It satisfies the ISO/IEC frequency band($860{\sim}960MHz$) and is also applicable to mobile RFID readers. A VCO is designed to operate at 1.8GHz band such that the LO pulling effect is minimized. The 900MHz differential I/Q LO signals are obtained by dividing the differential signal from an integrated 1.8GHz VCO. It is designed using a $0.18{\mu}m$ RF CMOS process. The measured results show that the designed circuit has a phase noise of -103dBc/Hz at 100KHz offset and consumes 9mA from a 1.8V supply. The channel switching time of $10{\mu}s$ over 5MHz transition have been achieved, and the chip size including PADs is $1.8{\times}0.99mm^2$.

• 한국전기전자재료학회논문지
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• 제16권1호
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• pp.83-87
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• 2003

In the present paper we suggested a parallel branch structure of aluminum spiral inductor for the use of RF integrated circuit at 1∼3 GHz. The inductor was implemented on p-type silicon wafer (5∼15Ω-cm) under the standard CMOS process and it showed a enhanced qualify(Q) factor by more than 10 % with no degradation of inductance. The effect of the structure modification on the Q factor and the inductance was scrutinized comparing with conventional spital inductors

• 반도체디스플레이기술학회지
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• 제2권1호
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• pp.11-14
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• 2003

The high Q(quality factor) suspended spiral inductors were fabricated on the silicon substrate by 3D surface micromachined process. The integration of 2.4GHz VCO has been performed by fabricating suspended spiral inductor of the top of CMOS VCO circuit. The phase noise of VCO integrated MEMS inductor is 93.5 dBc/Hz at 100kHz of offset frequency.

• ETRI Journal
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• 제42권5호
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• pp.781-789
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• 2020

In this study, an E-band low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) has been designed using silicon-germanium 130-nm bipolar complementary metal-oxide-semiconductor technology to suppress unwanted signal gain outside operating frequencies and improve the signal gain and noise figures at operating frequencies. The proposed impedance-controllable filter has series (R_s) and parallel (R_p) resistors instead of a conventional inductor-capacitor (L-C) filter without any resistor in an interstage matching circuit. Using the impedance-controllable filter instead of the conventional L-C filter, the unwanted high signal gains of the designed E-band LNA at frequencies of 54 GHz to 57 GHz are suppressed by 8 dB to 12 dB from 24 dB to 26 dB to 12 dB to 18 dB. The small-signal gain S₂₁ at the operating frequencies of 70 GHz to 95 GHz are only decreased by 1.4 dB to 2.4 dB from 21.6 dB to 25.4 dB to 19.2 dB to 24.0 dB. The fabricated E-band LNA MMIC with the proposed filter has a measured S₂₁ of 16 dB to 21 dB, input matching (S₁₁) of -14 dB to -5 dB, and output matching (S₂₂) of -19 dB to -4 dB at E-band operating frequencies of 70 GHz to 95 GHz.

• International journal of advanced smart convergence
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• 제11권4호
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• pp.96-103
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• 2022

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm². In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

• 한국전기전자재료학회논문지
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• 제27권6호
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• pp.356-360
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• 2014

In this paper, the effect of underpass structure on quality factor and breakdown voltage of octagonal inductors which were fabricated with 90 nm complementary metal-oxide-semiconductor (CMOS) technology for radio frequency integrated circuit (RFIC) was studied. It was found that quality factor and breakdown voltage of inductors with more than one metal layer for underpass showed improved properties compared to those with one metal layer. However, little change of quality factor and breakdown voltage was observed between the inductors with two and more than two metal layers for underpass. Therefore, underpasses with two metal layers are promising for RFIC designs of the octagonal inductors in 90 nm CMOS technology.