• ETRI Journal
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• v.30 no.1
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• pp.33-46
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• 2008

This paper presents the experimental results of a low-power low-cost RF transceiver for the 915 MHz band IEEE 802.15.4b standard. Low power and low cost are achieved by optimizing the transceiver architecture and circuit design techniques. The proposed transceiver shares the analog baseband section for both receive and transmit modes to reduce the silicon area. The RF transceiver consumes 11.2 mA in receive mode and 22.5 mA in transmit mode under a supply voltage of 1.8 V, in which 5 mA of quadrature voltage controlled oscillator is included. The proposed transceiver is implemented in a 0.18 ${\mu}m$ CMOS process and occupies 10 $mm^2$ of silicon area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.2
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• pp.111-116
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• 2003

In this paper, a CMOS baseband analog receiver for wireless home network is discussed. It is composed of a Gilbert type mixer, an Elliptic 6th order 1ow pass filter, and a 6-bit A/D converter. The main role of the mixer is generating a mixed analog signal between the 200MHz output signal of CMOS RF stage and the 199MHz local oscillator. After the undesired high frequency component of the mixed signal comes out. Finally, the analog signal is converted into digital code at the 6-bit A/D converter, The proposed receiver is fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly 5-metal CMOS technology, and the chip area is 200${\mu}{\textrm}{m}$ X1400${\mu}{\textrm}{m}$. the receiver consumes 130㎽ at 2.5V power supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.449-455
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• 2004

This paper presents a novel defect detection method for one chip RF front end with fault detection circuits using input matching measurement. We present a BIST circuit using 40.25{\mu}m$ CMOS technology. We monitor the input transient voltage of the RF front end to differentiate faulty and fault-free RF front end. Catastrophic as well as parametric variation fault models are used to simulate the faulty response of the RF front end. This technique has several advantages with respect to the standard approach based on current test stimulus and frequency domain measurement. Because DUT and fault detection circuits are implemented in the same chip, this test technique only requires use of digital voltmeter (RMS meter) and RF voltage source generator for simpleand inexpensive testing.

• Journal of Positioning, Navigation, and Timing
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• v.4 no.3
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• pp.115-122
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• 2015

Global Positioning System (GPS) is used in various fields such as communications systems, transportation systems, e-commerce, power plant systems, and up to various military weapons systems recently. However, GPS receiver is vulnerable to jamming signals as the GPS signals come from the satellites located at approximately 20,000 km above the earth. For this reason, various anti-jamming techniques have been developed for military application systems especially and it is also required for commercial application systems nowadays. In this paper, we proposed a dual-channel Global Navigation Satellite System (GNSS) RF ASIC for digital pre-correlation anti-jam technique. It not only covers all GNSS frequency bands, but is integrated low-gain/attenuation mode in low-noise amplifier (LNA) without influencing in/out matching and 14-bit analogdigital converter (ADC) to have a high dynamic range. With the aid of digital processing, jamming to signal ratio is improved to 77 dB from 42 dB with proposed receiver. RF ASIC for anti-jam is fabricated on a 0.18-μm complementary metal-oxide semiconductor (CMOS) technology and consumes 1.16 W with 2.1 V (low-dropout; LDO) power supply. And the performance is evaluated by a kind of test hardware using the designed RF ASIC.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.270-275
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• 2012

This paper describes design of a variable-N frequency synthesizer for RF PLL with $0.13{\mu}m$ silicon CMOS technology being used as an application of the UWB system like MBOA. To get good performance of speed and noise super dynamic circuits was used, and to get variable-N division ratio MOSFET switching circuits was used. Especially to solve narrow bandwidth problem of the dynamic circuits load resistance value of unit divider block was varied. Simulation results of the designed circuit shows very fast and wide operation characteristics as 5~26GHz frequency range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.56-61
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• 2011

This paper describes design of a programmable frequency synthesizer for RF PLL with $0.18{\mu}m$ silicon CMOS technology being used as an application of the UWB system like MBOA. To get good performance of speed and noise super dynamic circuits was used, and to get programmable division ratio switching circuits was used. Especially to solve narrow bandwidth problem of the dynamic circuits load resistance value of unit divider block was varied. Simulation results of the designed circuit shows very fast and wide operation characteristics as 1~14GHz frequency range.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

This paper presents a new low-cost fault-based Built-In Self-Test (BIST) scheme and technique for 1.8GHz RF receiver front end. The technique utilizes input impedance matching measurement. The BIST block and RF receiver front end are designed using 0.25m CMOS technology on a single chip. The technique is simple and inexpensive. The overhead of the BIST circuit is approximately $10\%$ of the total area of the RF front end.

• ETRI Journal
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• v.27 no.5
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• pp.579-584
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• 2005

A CMOS direct-conversion mixer with a single transistor-level topology is proposed in this paper. Since the single transistor-level topology needs smaller supply voltage than the conventional Gilbert-cell topology, the proposed mixer structure is suitable for a low power and highly integrated RF system-on-a-chip (SoC). The proposed direct-conversion mixer is designed for the multi-band ultra-wideband (UWB) system covering from 3 to 7 GHz. The conversion gain and input P1dB of the mixer are about 3 dB and -10 dBm, respectively, with multi-band RF signals. The mixer consumes 4.3 mA under a 1.8 V supply voltage.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.505-508
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• 2004

Gate length dependent data of intrinsic MOSFET equivalent circuit parameters are extracted using a direct extraction technique based on simple 2-port parameter equations. The relatively scalable data with respect to gate length are obtained. These data are verified to be acrurate by observing good correspondence between modeled and measured S-parameters up to 30GHz. These data will be helpful to construct RF scalable MOSFET model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.45-52
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• 2008

We investigated the design of an RF-powered, wireless temperature sensor tag chip using $0.18-{\mu}m$ CMOS technology. The transponder generates its own power supply from small incident RF signal using Schottky diodes in voltage multiplier. Ambient temperature is measured using a new low-power temperature-to-voltage converter, and an 8-bit single-slope ADC converts the measured voltage to digital data. ASK demodulator and digital control are combined to identify unique transponder (ID) sent by base station for multi-transponder applications. The measurement of the temperature sensor tag chip showed a resolution of $0.64^{\circ}C/LSB$ in the range from $20^{\circ}C$ to $100^{\circ}C$, which is suitable for environmental temperature monitoring. The chip size is $1.1{\times}0.34mm^2$, and operates at clock frequency of 100 kHz while consuming $64{\mu}W$ power. The temperature sensor required a -11 dBm RF input power, supported a conversion rate of 12.5 k-samples/sec, and a maximum error of $0.5^{\circ}C$.