• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.9
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• pp.1045-1049
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• 2010

In this paper, we proposed an ultra-low power low noise amplifier(LNA) using a TSMC 0.18 ${\mu}m$ RF CMOS process. To satisfy the low power consumption with high gain, a current-reused technique is utilized. In addition, a low bias voltage in the subthreshold region is utilized to achieve ultra low power characteristic. The designed LNA has the voltage gain of 13.8 dB and noise figure(NF) of 3.4 dB at 2.4 GHz. The total power consumption of the designed LNA is only 0.63 mW from 0.9 V supply voltage and chip occupies $1.1\;mm{\times}0.8\;mm$ area.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.671-674
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• 1998

본 논문에서는 최근 급격히 수요가 증대하고 있는 휴대용 단말기의 수신기 선단에 사용되는 저잡음 증폭기(LNA)를 0.6㎛ CMOS공정 파라미터를 사용하여 설계하였다. 설계된 LNA는 전원 전압 ±1.2v, 900㎒대에서 동작하는 전류 재사용방식의 적층 CMOS구조로서 시뮬레이션 결과 전력소모가 9.45㎽, 전력이득은 23.7dB, 선형지수 OIP3는 7.6dBm을 나타내어 저전력 저잡음 특성을 얻었다. 사용된 인덕터의 Q는 3.5이다.

• ETRI Journal
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• v.42 no.6
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• ETRI Journal
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• v.21 no.4
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• pp.1-8
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• 1999

Thick metal 0.8${\mu}m$ CMOS technology on high resistivity substrate(RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15mA that is an excellent noise performance compared with the offchip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integrating of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatibel process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.106-113
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• 2003

In this paper, we proposed low noise amplifier for 2.4GHz ISM frequency with CMOS technology. The property of noise and gain is improved by cascode architecture. The architecture, which common source output of cascode is connected to input of parallel MOS, reduce IM. The LNA results based on Hynix 0.35${\mu}{\textrm}{m}$ 2poly 4metal CMOS processor with a 3.3V supply. It achieves a gain of 13dB, noise figure of 1.7dB, IP3 of 8dBm, Input/output matching of -31dB/-28dB, reverse isolation of -25dB. and power dissipation of 4.7mW with HSPICE simulation. The size of layout is smaller than 2 ${\times}$ 2mm with Mentor.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.199-207
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• 2011

A Ku-band low noise amplifier has been designed and fabricated by using 0.25 um SiGe BiCMOS process. The developed Ku-band LNA RFIC which has been designed with hetero-junction bipolar transistor(HBT) in the BiCMOS process have noise figure about 2.0 dB and linear gain over 19 dB in the frequency range from 9 GHz to 14 GHz. Optimization technique for p-tap value and electro-magnetic(EM) simulation technique had been used to overcome the inaccuracy in the PDK provided from the foundry service company and to supply the insufficient inductor library. The finally fabricated low noise amplifier of two fabrication runs has been implemented with the size of $0.65\;mm{\times}0.55\;mm$. The pure amplifier circuit layout with the reduced size of $0.4\;mm{\times}0.4\;mm$ without the input and output RF pads and DC bais pads has been incorporated as low noise amplication stages in the multi-function RFIC for the active phased array antenna of Ku-band satellite VSAT.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.129-132
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• 2000

In this paper, a 1.8㎓ low noise amplifier was designed and simulated using 0.2$\mu\textrm{m}$ Si CMOS process. Noise characteristics and s parameters were extracted for the 300$\mu\textrm{m}$ gate width and 0.25$\mu\textrm{m}$ gate length NMOS transistors. For high available power gain, each stage was designed cascode type. It revealed available power gain of 23.5dB, noise figure of 2.0dB, power consumption of 15㎽ at 2.5V. It was shown that designed low noise amplifier had good RF performance. Designed Si CMOS LNA is expected to be used for RF front-end in transceiver.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.333-336
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• 2000

This paper describes a CMOS low noise amplifier (LNA) with bias current reusing architecture intended lot use in the front-end of IMT-2000 receiver. It has been implemented in a 0.35$\mu\textrm{m}$ CMOS process with two poly and four metal layers. In order to accuracy of simulation, we considered a bonding wire and a pad effect and used the measurements of capacitors and on-chip inductors which implemented in the same process. The LNA has a forward gain (S21) of 17 ㏈ and a noise fjgure of 1.26 ㏈. And it has a third-order intermodulation intercept point (IP3) of +3.15 ㏈m and a 1㏈ compression point (P1㏈) of -16 ㏈m, input referred, respectively. The power consumption is 19 ㎽ from a 3V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.6
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• pp.893-899
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• 2000

A 900 MHz low-noise amplifier(LNA) with a measured noise figure of 4.8 dB and an associated gain of 13.2 dB was fabricated in a 0.65 $\mu$m CMOS. The inductive source architecture of offers the possibility of achieving the best noise performance. At 900 MHz, the fabricated LNA dissipates 39 mW from a single 3 V power supply including the bias circuitry and provides -26dB input return loss, -17 dB output return loss, and an input 1-dB compression level of -12 dBm.

• 한국ITS학회:학술대회논문집
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• v.2006 no.10
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• pp.300-303
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• 2006