• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.32-36
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• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a 0.25-$\mu\textrm{m}$ standard CMOS process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier. Total power dissipation is 7.5 mW.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.35-40
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• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1312-1315
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• 2002

This research describes the design of a fully integrated fractional-N frequency synthesizer intended for the local oscillator in IMT-2000 system using 0.18-$\mu\textrm{m}$ CMOS technology and 1.8-V single power supply. The designed fractional-N synthesizer contains following components. Modified charge pump uses active cascode transistors to achieve the high output impedance. A multi-modulus prescaler has modified ECL-like D flip-flop with additional diode-connected transistors for short transient time and high frequency operation. And phase-frequency detector, integrated passive loop filter, LC-tuned VCO having a tuning range from 1.584 to 2.4 ㎓ at 1.8-V power supply, and higher-order sigma-delta modulator are contained. Finally, designed frequency synthesizer provides 5 ㎒ channel spacing with -122.6 dBc/Hz at 1 ㎒ in the WCDMA band and total output power is 28 mW.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.499-500
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• 2006

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.

• International Journal of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.122-128
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• 2023

This paper proposes two kinds of single-balanced direct conversion quadrature receivers using selfoscillating LMVs in which the voltage-controlled oscillator (VCO) itself operates as a mixer while generating an oscillation. The two LMVs are complementary coupled and series coupled to generate the quadrature oscillating signals, respectively. Using a 65 nm CMOS technology, the proposed quadrature receivers are designed and simulated. Oscillating at around 2.4 GHz frequency, the complementary coupled quadrature receiver achieves the phase noise of -28 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The other series coupled receiver achieves the phase noise of -31 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain of the two single-balanced receivers is 37 dB and 45 dB, respectively. The double-sideband noise figure of the two receivers is 5.3 dB at 1 MHz offset. The quadrature receivers consume about 440 μW dc power from a 1.0-V supply.

• Journal of Sensor Science and Technology
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• v.28 no.2
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• pp.121-126
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• 2019

The voltage-controlled oscillator is one of the fundamental building blocks that determine the signal quality and power consumption in RF transceivers for wireless sensor networks. Ring oscillators are attractive owing to their small form factor and multi-phase capability despite the relatively poor phase noise performance in comparison with LC oscillators. The phase noise of a ring oscillator can be improved by using a coupled structure that works at a lower frequency. This paper introduces a 2.4 GHz low-noise ring oscillator that consists of two 3-stage coupled ring oscillators. Each sub-oscillator operates at 800 MHz, and the multi-phase signals are combined to generate a 2.4 GHz quadrature output. The voltage-controlled ring oscillator designed in a 65-nm standard CMOS technology has a tuning range of 800 MHz and exhibits the phase noise of -104 dBc/Hz at 1 MHz offset. The power consumption is 13.3 mW from a 1.2 V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.