• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.64-69
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• 2013

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.10
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• pp.93-97
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• 2005

We have developed the FDSS (Fine Digital Sun Sensor) for the space technology of the STSAT-2 (Seience & Technology Satellite 2). The FDSS is firstly developed by using CMOS image sensor(CIS) in South Korea. The FDSS consists of the optics part, FPGA(Field Programable Gate Array) part, and MCU(Micro controller unit)part. This paper will focus on the optical characteristics of the optics part and describe the configuration of FDSS with the design of aperture. We also analyze the characteristic of optics about the pixel of the CMOS image sensor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.104-110
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• 2011

A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.110-119
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• 2017

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

• Journal of Sensor Science and Technology
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• v.26 no.4
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• pp.223-227
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• 2017

Conventional CMOS image sensors (CISs) have a trade-off relationship between dynamic range and sensitivity. In addition, their sensitivity is determined by the photodiode capacitance. In this paper, CISs that consist of dual-sensitivity photodiodes in a unit pixel are proposed for achieving wide dynamic ranges. In the proposed CIS, signal charges are generated in the dual photodiodes during integration, and these generated signal charges are accumulated in the floating-diffusion node. The signal charges generated in the high-sensitivity photodiodes are transferred to the input of the comparator through an additional source follower, and the signal voltages converted by the source follower are compared with a reference voltage in the comparator. The output voltage of the comparator determines which photodiode is selected. Therefore, the proposed CIS composed of dual-sensitivity photodiodes extends the dynamic range according to the intensity of light. A $94{\times}150$ pixel array image sensor was designed using a conventional $0.18{\mu}m$ CMOS process and its performance was simulated.

• Journal of Sensor Science and Technology
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• v.28 no.2
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• pp.71-75
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• 2019

This paper proposes the extension of the dynamic range in complementary metal oxide semiconductor (CMOS) image sensors (CIS) using switching operation of in-pixel inverter. A CMOS inverter is integrated in each unit pixel of the proposed CIS for switching operations. The n+/p-substrate photodiode junction capacitances are added to each unit pixel. When the output voltage of the photodiode is less than half of the power supply voltage of the CMOS inverter, the output voltage of the CMOS inverter changes from 0 V to the power supply voltage. Hence, the output voltage of the CMOS inverter is adjusted by changing the supply voltage of the CMOS inverter. Thus, the switching point is adjusted according to light intensity when the supply voltage of the CMOS inverter changes. Switching operations are then performed because the CMOS inverter is integrated with in each unit pixel. The proposed CIS is composed of a pixel array, multiplexers, shift registers, and biasing circuits. The size of the proposed pixel is $10{\mu}m{\times}10{\mu}m$. The number of pixels is $150(H){\times}220(V)$. The proposed CIS was fabricated using a $0.18{\mu}m$ 1-poly 6-metal CMOS standard process and its characteristics were experimentally analyzed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.246-251
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• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.465-471
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• 2023

This paper proposes a comparator structure that improves the noise and output delay of a single-slope ADC(SS-ADC) used in CMOS Image Sensor (CIS). To improve the noise and delay characteristics of the output, a comparator structure using the miller effect is designed by inserting a capacitor between the output node of the first stage and the output node of the second stage of the comparator. The proposed comparator structure improves the noise, delay of the output, and layout area by using a small capacitor. The CDS counter used in the single slop ADC is designed using a T-filp flop and bitwise inversion circuit, which improves power consumption and speed. The single-slope ADC also performs dual CDS, which combines analog correlated double sampling (CDS) and digital CDS. By performing dual CDS, image quality is improved by reducing fixed pattern noise (FPN), reset noise, and ADC error. The single-slope ADC with the proposed comparator structure is designed in a 0.18-㎛ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.65-70
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• 2006

An image sensor has limited dynamic range while the human eye has logarithmic response over wide range of light intensity. Although the sensor gain can be set high to identify details in darker area on the image, this results in saturation in brighter area. The gamma correction is essential to fit the human eye response. However, the digital gamma correction degrades image quality especially for darker area on the image due to the limited ADC resolution and the dynamic range. This Paper proposes a CMOS image sensor (CIS) with a nonlinear analog-to-digital converter (AU) which performs analog gamma correction. The CIS with the proposed nonlinear analog-to-digital conversion scheme was fabricated with a $0.35{\mu}m$ CMOS process. The analog gamma correction using the proposed nonlinear ADC CIS provides the 2.2dB peak-signal-to-noise-ratio(PSM) improved image qualify than conventional digital gamma correction. The PSNR of the image obtain from the digital gamma correction is 25.6dB while it is 27.8dB for analog gamma correction. The PSNR improvement over digital gamma correction is about $28.8\%$.