• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.69-76
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• 2008

This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.449-455
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• 2004

This paper presents a novel defect detection method for one chip RF front end with fault detection circuits using input matching measurement. We present a BIST circuit using 40.25{\mu}m$ CMOS technology. We monitor the input transient voltage of the RF front end to differentiate faulty and fault-free RF front end. Catastrophic as well as parametric variation fault models are used to simulate the faulty response of the RF front end. This technique has several advantages with respect to the standard approach based on current test stimulus and frequency domain measurement. Because DUT and fault detection circuits are implemented in the same chip, this test technique only requires use of digital voltmeter (RMS meter) and RF voltage source generator for simpleand inexpensive testing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.