• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.47-55
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• 1996

An optical transmitter, which is a key component of the optical transmission system, converts the electrical signal to optical signal and consists of a high-speed current-pulse driver for laser diode and low-speed feedback loops that stabilize optical power against aging, power supply voltage fluctuations, and ambient temperature changes. In this paper, the power-stabilizing part, which forms the bulk of the optical transmitter circuitry was designed in integrted circuits. Operational amplifiers and reference voltage generation circuits, which were identified as key building blocks for the power-stabilizing feedback loops, were designed and were subsequently verified through HSPICE simulations. The designed operational amplifier consists of a two-stage folded cascode amplifier and class AB output stage, whereas the reference voltage is obtained by bandgap reference circuits. Finally the power-stabilizing circuitry was laid out based on 3\mu$m CMOS design rules for fabrication.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.04a
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• pp.485-488
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• 2007

최근 Analog Sampled-Data 신호처리를 위하여 주목되고 있는 SI(Switched-Current) circuit은 저전력 동작을 하는 장점이 있지만, 반면에 SI circuit에서의 기본 회로인 Current Memory는 Charge Injection에 의한 Clock Feedthrough이라는 치명적인 단점을 갖고 있다. 따라서 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 일반적인 해결방안으로 Dummy Switch의 연결을 검토하였고, Austria Mikro Systeme(AMS)에서 $0.35{\mu}m$ CMOS process BSIM3 Model로 제작하기 위하여 Current Memory의 Switch MOS와 Dummy Switch MOS의 적절한 Width을 정의하여야 하므로, 그 값을 도출하였다. Simulation 결과, Switch의 Width는 $2{\mu}m$, Dummy Switch의 Width는 $2.35{\mu}m$로 정의될 수 있음을 확인하였다.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1660-1661
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• 2011

본 논문에서는 7중 대역 (GSM850, GSM900, DCS1800, PCS1900, UMTS850, UMTS1900, UMTS2100) 을 지원하는 LPF 내장형 LTCC 프런트 엔드 모듈 (FEM) 을 설계, 제작 및 측정하였다. 제작된 FEM은 효과적인 고조파 제거를 위해 수동소자를 LTCC 기판에 내장하여 저역 통과 필터(LPF)를 구현하였다. 본 논문에서 제안하는 FEM은 송수신 신호를 선택하기 위한 flip-chip 형태의 CMOS RF SP9T switch, Rx 신호의 수신을 위한 dual type의 SAW filter, 매칭 및 ESD 보호 회로를 위한 0603 크기의 칩소자가 부품 외부에 실장되어 구현된다. 전체 크기는 $4.5{\times}3.2{\times}1.2\;mm^3$의 초소형으로 내부 GND 2개 층을 포함하여 총 16층으로 구성된다. 측정결과는 송신단과 수신단의 삽입손실이 각각 1.7 dB, 3.6 dB 이하의 우수한 특성을 보였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.4
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• pp.443-449
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• 2010

Current testing is an effective method which offers higher fault detection and diagnosis capabilities than voltage testing. Since current testing requires much longer testing time than voltage testing, it is important to note that a fault is untestable if the two nodes have same values at all times. In this paper, we present an object oriented fault detection scheme for various fault models using current testing. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method in reducing the number of faults and its usefulness in various fault models.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.375-377
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• 2006

A Analog parallel processing-based Viterbi decoder which decodes PRML signal of DVD has been designed by CMOS circuit. The analog processing-based Viterbi decoder implements are functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The Analog parallel processing-based Viterbi decoding technology is applied for the PR(1,2,2,1) signal decoding of DVD. The benefits are low power consumption and less silicon consumption. In this paper, the comparison of the Analog parallel processing-based Viterbi Decoder which has a function of the error correction between Max operation and Average operation is discussed.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.100-106
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• 1999

A new IBC(Island Body Contact) structure is introduced to SOI CMOS VLSI for stabilizing the body potential of the MOSFET without the additional area consumption. The improvement of the body contact effect is achieved by reducing the body resistance and the area is saved as the bodies of the MOSFETs are connected together. Its property as VLSI device is confirmed through the device simulations and the measurement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.3B
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• pp.362-368
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• 2001

본 논문에서는 두 개의 17비트 오퍼랜드를 radix-4 Booths 알고리즘을 이용하여 곱셈 연산을 수행하는 곱셈기를 설계하고 효율적인 풀커스팀 디자인에 대한 테스트 방법을 제안하였다. 클럭 속도를 빠르게 하기 위하여 2단파이프라인 구조로 설계하고 규칙적인 레이아웃을 위해 4:2 CSA(Carry Save Adder)를 사용하였다. 회로는 LG 반도체의 0.6-um 3-Metal N-well CMOS 공정을 사용하여 칩으로 제작되었다. 새로운 개념의 모듈레벨 고착 고장 모델을 제안하였고 제안한 테스트 방법을 사용하여 관찰해야 하는 노드의 수를 약 88% 줄여 효율적인 고장 시뮬레이션을 수행하였다. 설계된 곱셈기는 9115개의 트랜지스터로 구성되며 코어 부분의 레이아웃 면적은 약 1135*1545 um2 이다. 제작된 칩은 전원접압 5V에서 약 24MHz의 클럭 주파수로 동작한다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.573-574
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• 2008

In this paper, we propose a mixed driving circuit for the source driver of QVGA-scale TFT-LCD driver IC to reduce the area of the source driver. In the mixed driving circuit, graphic data pass or go through the mixed channel driver whether RGB data are the same or not. The mixed driving circuit has been designed in transistor level using the 0.35um CMOS technology and has been verified using Hspice.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.585-586
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• 2008

In this paper, a novel beta-multiplier reference current source circuit for the 800mV power-supply voltage is presented. In order to cope with the narrow input common-mode range of the OpAmp in the reference circuit, shunt resistive voltage divider branches were deployed. High gain OpAmp was designed to compensate intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18um CMOS process with nominal Vth of 420mV and -450mV for nMOS and pMOS transistor respectively. The total power consumption including OpAmp is less than 50uW.