• The Journal of the Acoustical Society of Korea
• /
• v.16 no.3
• /
• pp.106-113
• /
• 1997

A 3V CMOS continuous-time fully-balanced integrator for low-voltage analog-digital mixed-mode signal processing is designed in this paper. The basic architecture of the designed fully-balanced integrator is complementary circuit which is composed of NMOS and PMOS transistor. And this complementary circuit can extend transconductance of an integrator. So. the unity gain frequency, pole and zero of integrator are increased by the extended transconductance. The SPICE simulation and small signal analysis results show that the UGF, pole and zero of the integrator is increased larger than those of the compared integrtors. The three-pole active low-pass filter is designed as a application circuit of the fully-balanced integrator, using 0.83V CMOS processing parameter.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.6 s.360
• /
• pp.1-7
• /
• 2007

This paper proposes CMOS semi-digital data recovery with 2X converse oversampling to reduce power consumption and chid area of high definition multimedia interface (HDMI) receivers. Proposed recovery can reduce its power and the effective area by using nt converse oversampling algorithm and semi-digital architecture. Proposed circuit is fabricated using 0.18um CMOS process and measured results demonstrated the power consumption of 14.4mW, the effective area of $0.152mm^2$ and the jitter tolerance of 0.7UIpp with 1.8V supply voltage.)

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.5
• /
• pp.359-369
• /
• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.3 s.357
• /
• pp.65-71
• /
• 2007

We propose a pixel-level automatic calibration circuit scheme that initializes a capacitive fingerprint sensor LSI to eliminate the influence of the surface condition and environment, which is degraded by dirt during long-time use, process variation and ambient temperature. The sample chip is fabricated on $0.35{\mu}m$ standard CMOS process. The calibration is executed by optimizing the reference voltage in each pixel to make the sensor signals of all pixels the same. The calibration control circuit is composed of the sensing circuit and charge pumping circuit, and calibrates all pixels in a short time. 16-level gray scale fingerprint images can be captured to increase the accuracy of identification. This confirms that the scheme is effective for capturing consistent clear images during long-time use.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.691-692
• /
• 2016

본 논문은 802.11a 무선 랜용 5.25-GHz BiCMOS 저 잡음 증폭기를 제안한다. 이러한 회로는 1볼트 전원에서 동작하며, 저 전압 전원 공급에서도 높은 전압 이득을 가지도록 설계하였다. 제안한 회로는 $0.18{\mu}m$ SiGe HBT BiCMOS로 설계되어 있다. 저 전압 및 저 전력 동작을 위해 바이어스 회로는 밴드 갭 참조 (band-gap reference circuit) 바이어스 회로를 사용하였다. 제안한 회로는 최근 발표된 연구결과에 비해 높은 전압이득, 낮은 잡음지수 및 작은 칩 크기 특성을 보였다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.5C
• /
• pp.378-385
• /
• 2008

This paper has been designed with CMOS Analog-to-Digital Converter(ADC) to use a high speed embedded system. It used flash ADC with a voltage estimator and comparator for background developed autozeroing. The speed of this architecture is almost similar to conventional flash ADC but the die size are lower due to reduced numbers of comparators and associated circuity. This ADC is implemented in a $0.25{\mu}m$ pure digital CMOS technology.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.15 no.3
• /
• pp.479-486
• /
• 2020

In this paper, we present a design method for improving the linearity and dynamic range of the analog current mode multiplier circuit, which is one of the key devices in an analog current mode AI processor. The proposed circuit consists of 4 quadrant translinear loops made up of NMOS transistors only, which minimizes physical mismatches of the transistors. The proposed circuit can be implemented at 117㎛ × 109㎛ in 0.35㎛ CMOS process and has a total harmonic distortion of 0.3%. The proposed analog current mode multiplier is expected to be useful as the core circuit of a current mode AI processor.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.28-36
• /
• 2008

This paper describes a low-power CMOS analog front-end block for UHF band RFID tag chips. It satisfies ISO/IEC 18000-6C and includes a memory block for test. For reducing power consumption, it operates with an internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator can more exactly demodulate than conventional demodulator with low current consumption. It is designed using a $0.18{\mu}m$ CMOS technology. Measurement results show that it can operate properly with an input as low as $0.25V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.11
• /
• pp.29-34
• /
• 1999

In this paper, a current comparative frequency automatic tuning circuit for the CMOS gm-C bandpass filters are designed with the new architecture. And also, when the designed circuit is compared to the typical tuning circuit, the designed circuit has very simple architecture that is composed of the current comparator and charge pump and operating in 3V power supply. The proposed tuning circuit automatically compensates the difference between the operating current of the transconductor and the specified reference Current. Using CMOS 0.8um parameter a biquad gm-C bandpass filter with center frequency($f_\circ$=60MHz) is designed, and according to the transistor size the variation of the center frequency is simulated. As the HSPICE simulation results, the tuning operation of the proposed current comparative frequency automatic tuning circuit is verified.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.412-415
• /
• 2015

This paper presents a MPPT(Maximum Power Point Tracking) control CMOS interface circuit for vibration energy harvesting. The proposed circuit consists of an AC-DC converter, MPPT Controller, DC-DC boost converter and PMU(Power Management Unit). The AC-DC converter rectifies the AC signals from vibration devices(PZT). MPPT controller is employed to harvest the maximum power from the PZT and increase efficiency of overall system. The DC-DC boost converter generates a boosted and regulated output at a predefined level and provides energy to load using PMU. A full-wave rectifier using active diodes is used as the AC-DC converter for high efficiency, and a schottky diode type DC-DC boost converter is used for a simple control circuitry. The proposed circuit has been designed in a 0.35um CMOS process. The chip area is $950um{\times}920um$.