• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.10
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• pp.1001-1008
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• 1991

.In this paper the efficient clock recovery algorithm is proposed to regenerate the manchester code at the system using the Manchester encoding scheme such as LAN. Mobile communication and digital communication systems. The proposed clock recovery circuit recovers the clock using the two times of the same original transmitted frequency can be completely recovered. The implementation of the proposed clock recovery circuit and the interpretation of test results prove the validity of the proposed algorithm.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.771-774
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• 2014

지난 몇 년간 스마트폰은 굉장히 빠른 속도로 발전하면서 생활 속에서 큰 비중을 차지하고 있다. 이러한 스마트폰에는 에너지 효율, 크기, 속도 면에서 모바일 기기에 적합한 Flash storage가 탑재되고 있다. 이 논문에서는 스마트폰에 탑재된 Flash storage를 기반으로 한 버퍼 교체 알고리즘들 가운데 Spatial Clock 알고리즘에 초점을 맞추고 있다. 그리고 이 알고리즘이 Video Streaming workload에서 성능 발휘를 하지 못한다는 점을 해결하기 위해 SWSC(Sequential Write Spatial Clock) 알고리즘을 제안하였다. 이 알고리즘은 dirty 페이지들이 연속적인 경우 sequential write를 수행한다. 따라서 write 수행시간을 줄일 수 있고 결과적으로 Video Streaming workload에서도 좋은 성능을 발휘할 수 있다.

• The KIPS Transactions:PartD
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• v.16D no.6
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• pp.825-834
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• 2009

최근에 낸드 플래시 메모리는 빠른 접근속도, 저 전력 소모, 높은 내구성 등의 특성으로 인하여 차세대 대용량 저장 매체로 각광 받고 있다. 그러나 디스크 기반의 저장 장치와는 달리 비대칭적인 읽기, 쓰기, 소거 연산의 처리 속도를 가지고 있고 제자리 갱신이 불가능한 특성을 가지고 있다. 따라서 디스크 기반 시스템의 버퍼 교체 정책은 플래시 메모리 기반의 시스템에서 좋은 성능을 보이지 않을 수 있다. 이러한 문제를 해결하기 위해 플래시 메모리의 특성을 고려한 새로운 플래시 메모리 기반의 버퍼 교체 정책이 제안되어 왔다. 본 논문에서는 디스크 기반의 저장 장치에서 우수한 성능을 보인 CLOCK-Pro를 낸드 플래시 메모리의 특성을 고려하여 개선한 CLOCK-NAND를 제안한다. CLOCK-NAND는 CLOCK-Pro의 알고리즘에 기반하며, 추가적으로 페이지 접근 정보를 효율적으로 활용하기 위한 새로운 핫 페이지 변경을 한다. 또한, 더티인 핫 페이지에 대해 콜드 변경 지연 정책을 사용하여 쓰기 연산을 지연하며, 이러한 새로운 정책들로 인하여 낸드 플래시 메모리에서 쓰기 연산 횟수를 효율적으로 줄이는 우수한 성능을 보인다.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.943-946
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• 1999

In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given path-length skew bound. The algorithm onstructs a bounded-skew tree(BST) in two steps:(ⅰ) a bottom-up phase to construct a binary tree of shortest-distance feasible regions which represent the loci of possible placements of clock entry points, and (ⅱ) a top-down phase to determine the exact locations of clock entry points. Experimental results show that our clock routing algorithm, named BST/DME, can produce a set of solutions with skew and wirelength trade-off.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.43-50
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• 2004

The clock skew is one of the major constraints for high-speed operation of synchronous integrated circuits. In this paper, we propose a hierarchical partitioning based clock network design algorithm called Advanced Clock Tree Generation (ACTG). Especially new effective partitioning and refinement techniques have been developed in which the capacitance and edge length to each sink are considered from the early stage of clock design. Hierarchical structures obtained by parhtioning and refinement are utilized for balanced clock routing. We use zero skew routing in which Elmore delay model is used to estimate the delay. An overlap avoidance routing algorithm for clock tree generation is proposed. Experimental results show significant improvement over conventional methods.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.543-556
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• 2009

Recently, NAND flash memory is being used as the swap device of virtual memory as well as the file storage of mobile systems. Since temporal locality is dominant in page references of virtual memory, LRU and its approximated CLOCK algorithms are widely used. However, cost of a write operation in flash memory is much larger than that of a read operation, and thus a page replacement algorithm should consider this factor. This paper analyzes virtual memory read/write reference patterns individually, and observes the ranking inversion problem of temporal locality in write references which is not observed in read references. With this observation, we present a new page replacement algorithm considering write frequency as well as temporal locality in estimating write reference behaviors. This new algorithm dynamically allocates memory space to read/write operations based on their reference patterns and I/O costs. Though the algorithm has no external parameter to tune, it supports optimized implementations for virtual memory systems, and also performs 20-66% better than CLOCK, CAR, and CFLRU algorithms.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.64-74
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• 1999

A new clock skew optimization for clock routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevent the total wire length from increasing. As the clock skew is the major constraint for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization can increase total wire length, therefore clock routing is performed within the given skew bound which can not induce the malfunction. Clock routing under the specified skew bound can decrease total wire length Not only total wire length and delay time minimization algorithm using merging point relocation method but also clock skew reduction algorithm using link-edge insertion technique between two nodes whose delay difference is large is proposed. The proposed algorithm construct a new clock routing topology which is generalized graph model while previous methods uses only tree-structured routing topology. A new cost function is designed in order to select two nodes which constitute link-edge. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance difference is short. Furthermore, routing topology construction and wire sizing algorithm is developed to reduce clock delay. The proposed algorithm is implemented in C programming language. From the experimental results, we can get the delay reduction under the given skew bound.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.12
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• pp.913-917
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• 2009

Flash memories have asymmetric I/O costs for read and write in terms of latency and energy consumption. However, the ratio of these costs is dependent on the type of storage. Moreover, it is becoming more common to use two flash memories on a system as an internal memory and an external memory card. For this reason, buffer cache replacement algorithms should consider I/O costs of device as well as possibility of reference. This paper presents WWCLOCK(Write-Weighted CLOCK) algorithm which directly uses I/O costs of devices along with recency and frequency of cache blocks to selecting a victim to evict from the buffer cache. WWCLOCK can be used for wide range of storage devices with different I/O cost and for systems that are using two or more memory devices at the same time. In addition to this, it has low time and space complexity comparable to CLOCK algorithm. Trace-driven simulations show that the proposed algorithm reduces the total I/O time compared with LRU by 36.2% on average.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.10
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• pp.1004-1010
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• 2012

In this paper, we propose the algorithm which considers applying recently proposed clock synchronization techniques with quite high accuracy in a few wireless sensor networks researches to time synchronization algorithm for multi-static radar system and especially overcomes the limitation of previous theory, cannot be applied between nodes in non-line of sight (NLOS). Proposed scheme estimates clock skew and clock offset using recursive robust least M-estimator with information of time stamp observations. And we improve the performance of algorithm by tracking and suppressing the time delays difference caused by NLOS system. Futhermore, this paper derive the mean square error (MSE) to present the performance of the proposed estimator and comparative analysis with previous methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3A
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• pp.237-246
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• 2007

Clock Synchronization is one of the most basic factors to be considered when we implement an indoor synchronization network for indoor positioning. In this paper, we present a new synchronization algorithm which does not employ time stamps in order to reduce the hardware complexity and data overhead. In addition to that, we describe an algorithm that is designed to compensate the frequency drift giving an serious impact on the synchronization performance. The performance evaluation of the proposed algorithm is achieved by investigating MTIE (Maximum Time Interval Error) values through simulations. In the simulations, the frequency drift values of the practical oscillators are used. From the simulation results, it is investigated that we can achieve the synchronization performance under 10 ns when we use 1 second synchronization interval with 1 ns resolution and TCXOs (Tmperature Compensated Cristal Oscillators) both in the master clock and the slave clock.