• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.1
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• pp.3-10
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• 2012

In this paper, we propose a fault injection attack on stream cipher A5/3 used in GSM. The fault assumption of this attack is based on that of fault injection attacks proposed in FDTC'05 and CISC-W'10. This attack is applicable to A5/3 supporting 64/128-bit session key, respectively, and can recover the session key by using a small number of fault injections. These works are the first known key recovery attack results on A5/3.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1221-1230
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• 1990

This paper presents a code generation method and an effective handling algorithm of ingeger constant multiplication for RISC machines in compiler design. As RISC Architectures usually use faster and more simply formed instructions than CISC's and most RISC processors do not have an integer multiplication instruction, it is required an effective algorithm to process integer multiplication. For the proposed code generator, Portable C Compiler(PCC) is redesigned to be suitable for an RISC machine, and composed an addition chain is built up to allow fast execution of constant multiplication, a part of integer one whicch appears very frequency in code generation phase.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.520-528
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• 2000

he speed of microprocessor getting faster, the data transfer width between the microprocessor and the memory becomes a critical part to limit the system performance. So the study of the computer architecture with the high code density is cmerged. In this paper, a tentative Bi-Length Instruction Set Computer(BISC) that consists of 16 bit and 32 bit length instructions is proposed as the high code density 32 bit microprocessor architecture. The 32 bit BISC has 16 general purpose registers and two kinds of instructions due to the length of offset and the size of immediate operand. The proposed 32 bit BISC is implemented by FPGA, and all of its functions are tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit BISC are designed and verified. This paper also proves that the code density of 32 bit BISC is much higher than the one of traditional architecture, it accounts for 130~220% of RISC and 130~140% of CISC. As a consequence, the BISC is suitable for the next generation computer architecture because it needs less data transfer width. And its small memory requirement offers that it could be useful for the embedded microprocessor.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.35-38
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• 2004

In this paper, we aim to implement the embedded VoIP Phone based on EISC core Microcontroller. EISC is recently new microprocessor architecture, which contains both advantage of RISC and CISC. This advantages are desirably resulted in high code density, high performance and 16/32/64bit scalable instruction length. Also, we select the embedded system which can be guaranteed performance and economical efficiency for implementation that system. As the step of this research, we first study basic system for implementation of target system. Next, we construct the structure of embedded VoIP Phone based on 32bit EISC MCU efficiently. And then we realize that constructed system and verify the performance of that realized system by the test of voice communication in field.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.132-140
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• 1994

In this paper, we consider the area-minimal implementation of the instruction decoder for microprogrammed processors such as modern CISC-type microprocessor. We formulate it as a constrained output encoding problem and, based on simulated annealing algorithm, propose efficient heuristic solution methods both for PLA and multi-level implementation of the decoder. Experimental results on various examples show that our methods produce, on the average, 10~40% reduction of the number of product terms for the PLA implementations and 9.8~34.4% reduction of the number of literal for the multi-level implementations compared to the results of random encoding method.

• Journal of Information Processing Systems
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• v.7 no.1
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• pp.209-220
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• 2011

One of the major factors influencing the phenomenal growth of the smart phone market is the active development applications based on open environments. Despite difficulties in finding and downloading applications due to the small screens and inconvenient interfaces of smart phones, users download applications nearly every day. Such user behavior patterns indicate the significance of smart phone applications. So far, studies on applications have focused mainly on technical approaches, including recommendation systems. Meanwhile, the issue of culture, as an aspect of user characteristics regarding smart phone use, remains largely unexamined throughout the world. Hence, the present study attempts to analyze the highest ranked smart phone applications downloaded and paid for that are ranked the highest in 10 countries (Korea, Japan, China, India, the UK, USA, Indonesia, Canada, France, and Mexico) and we then derive the CDSC (Cultural Dimensions Score of Content) for these applications. The results derived are, then, mapped to the cultural dimensions model to determine the CISC (Cultural Index Score for Country). Further, culturally significant differences in smart phone environments are identified using MDS analysis.

• Proceedings of the Korean Society of Computer Information Conference
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• 2022.07a
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• pp.263-266
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• 2022

최근 프로세서 제조공정의 급속한 발전으로 프로세서의 종류에 상관없이 같은 운영체제를 설치 할 수 있게 되었다. 하지만 근본적으로 프로세서의 종류에 따라 차이점이 있고, 동작방식이 다르기 때문에 포렌식 할 경우 같은 운영체제라도 다른 결과가 나올 수 있다. 본 논문은 디지털포렌식을 이용하여 CISC 프로세서의 Windows 운영체제와 RISC 프로세서의 Windows운영체제를 비교하고, 프로세서 방식에 따른 차이점을 통해 후속 연구 방향을 제시한다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.11-20
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• 1999

The data transfer width between the mocroprocessor and the memory comes to a critical part that limits system performance since the data transfer width has been as it was while the performance of a microprocessor is getting higher due to its continuous development in speed. And it is important that the memory should be in small size for the reduction of embedded microprocessor's price which is integrated on a single chip with the memory and IO circuit. In this paper, a mocroprocessor tentatively named as Extendable Instruction Set Computer(EISC) is proposed as the high code density 32 bit mocroprocessor architecture. The 32 bit EISC has 16 general purpose registers and 16 bit fixed length instruction which has the short length offset and small immediate operand. By using and extend register and extend flag, the offset and immediate operand could be extended. The proposed 32 bit EISC is implemented with an FPGA and all of its functions have been tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit EISC shows 140-220% and 120-140% higher code density than RISC and CISC respectively, which is much higher than any other traditional architectures. As a consequence, the EISC is suitable for the next generation computer architecture since it requires less data transfer width compared to any other ones. And its lower memory requirement will embedded microprocessor more useful.

• Steel and Composite Structures
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• v.13 no.2
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• pp.139-155
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• 2012

Serviceability rather than strength is the most critical design requirement for vibration-vulnerable floor constructions. Annoying vibrations due to normal walking activity have been observed more frequently on long-span lightweight floor systems in office and commercial retail buildings, raising the need for the development of floor vibration design procedures. This paper highlights some limitations of one of the most commonly used guidelines AISC/CISC DG11, and proposes improvements to this method. Design charts and approximate closed form formulas to estimate the walking response are developed in which various factors relating to the dynamic characteristics of both the floor and the excitation are considered. The accuracy of the proposed formulas and other proposals found in the literature is examined. The proposed modifications would be significant, especially with long-span floors where vibration levels may be underestimated by the current design procedure. The application of the proposed prediction method is illustrated by worked examples that reveal a good agreement with results obtained from finite element analyses and experiments. The presented work would enhance the accuracy and maintain the simplicity and convenience of the design guideline.

• Journal of Korea Multimedia Society
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• v.23 no.5
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• pp.641-649
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• 2020

As the usage of mobile devices extremely increases, malicious mobile apps(applications) that target mobile users are also increasing. It is challenging to detect these malicious apps using traditional malware detection techniques due to intelligence of today's attack mechanisms. Deep learning (DL) is an alternative technique of traditional signature and rule-based anomaly detection techniques and thus have actively been used in numerous recent studies on malware detection. In order to develop DL-based defense mechanisms against intelligent malicious apps, feeding recent datasets into DL models is important. In this paper, we develop a DL-based model for detecting intelligent malicious apps using KU-CISC 2018-Android, the most up-to-date dataset consisting of benign and malicious Android apps. This dataset has hardly been addressed in other studies so far. We extract OPcode sequences from the Android apps and preprocess the OPcode sequences using an N-gram model. We then feed the preprocessed data into LSTM and apply the concept of Information Gain to improve performance of detecting malicious apps. Furthermore, we evaluate our model with numerous scenarios in order to verify the model's design and performance.