• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.73-82
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• 2005

Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Therefore, this paper proposes a new test data compression/decompression method for low power testing. The method is based on analyzing the factors that influence test parameters: compression ratio, power reduction and hardware overhead. To improve the compression ratio and the power reduction ratio, the proposed method is based on Modified Statistical Coding (MSC), Input Reduction (IR) scheme and the algorithms of reordering scan flip-flops and reordering test pattern sequence in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data, not $T_{diff}$, and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.43-52
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• 2005

An prescaler which uses PLL(Phase Locked Loop) must satisfy high speed operation and low power consumption. Thus the performance or TSPC(True Single Phase Clocked) D-flip flops which is applied at Prescaler is very important. Power consumption of conventional TSPC D-flip flops was increased with glitches from output and unnecessary discharge at internal node in precharge phase. We proposed a new D-flip flop which reduced two clock transistors for precharge and discharge Phase. With inserting a new PMOS transistor to the input stage, we could prevent from unnecessary discharge in precharge phase. Moreover, to remove the glitch problems at output, we inserted an PMOS transistor in output stage. The proposed flip flop showed stable operations as well as low power consumption. The maximum frequency of prescaler by applying the proposed D-flip flop was 2.92GHz and achieved power consumption of 10.61mw at 3.3V. In comparison with prescaler applying the conventional TSPC D-flip $flop^[6]$, we obtained the performance improvement of $45.4\%$ in the view of PDP(Power-Belay-Product).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.83-89
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• 2006

This paper describes the design of I/Q channel 12bit Digital-to-Analog Converter(DAC) which shows the conversion rate of 120MHz and the power supply of 3.3V with 0.35um CMOS n-well 1-poly 4-metal process for advanced wireless transceiver. The proposed DAC utilizes 4-bit thermometer decoder with 3 stages for minimum glitch energy and linearity error. Also, using a optimized 4bit thermometer decoder for the decrement of the chip area. Integral nonlinearity(INL) of ${\pm}1.6LSB$ and differential nonlinearity(DNL) of ${\pm}1.3LSB$ have been measured. In single tone test, the ENOB of the proposed 12bit DAC is 10.5bit and SFDR of 73dB(@ Fs=120MHz, Fin=1MHz) is measured, respectively. Dual-tone test SFDR is 61 dB (@ Fs=100MHz, Fin=1.5MHz, 2MHz). Glitch energy of 31 pV.s is measured. The converter consumes a total of 105mW from 3.3-V power supply.

• Journal of Korea Foresty Energy
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• v.24 no.2
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• pp.1-9
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• 2005

After manufacturing fermentation system for degrading pig manure using environmentally friendly technique, performance of the system and characteristics of wood chips and pig manure fermented in the system were analyzed. Results from this study shows that proper fermentation temperature($55{\sim}60^{\circ}C$) reached 3days after the system started and degradation rate, which expresses fermentation performance of system, was $180{\iota}$/day. Even as progressing the fermentation of wood chips and pig manure mixture, the amount of extractives drawn out by alkali, and alcohol-benzene and lignin content was not varied. However, ash content in wood was increased. The inorganic compounds in pig manure seem to be transferred into wood chip. On the other hand holocellulose contents in wood were decreased a little. Holocellulose seems to be consumed as the second carbon source in fermentation process. Results through analysis of inorganic- and heavy metal elements contents in wood chips and pig manure fermented in long term process shows that inorganic elements($Ca^{2+},\;Mg^{2+},\;K^+,\;Na^+$ etc.) contents were increased with fermentation time and heavy metal elements(Cd, As, Cu etc.) which cause environmental pollution were not detected. Number of microorganisms including bacteria, actinomycetes, and fungi, the number of C.F.U(Colony Forming Unit) was increased while temperature in fermentation system was abruptly increased.

• Journal of Technologic Dentistry
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• v.34 no.2
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• pp.95-103
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• 2012

Purpose: Fracture strength of all-ceramic 3-unit fixed partial dentures manufactured by CAD/CAM and copy-milling systems were evaluated. Methods: Zirconia cores were made by milling the pre-sintered zirconia block by CAD/CAM or copy milling method followed by subsequent sintering. By building-up the corresponding porcelains on the core, all-ceramic bridges were fabricated, and those were evaluated in comparison with PFM fixed partial denture. Results: During the flexural test of the 3-unit PFM bridge, the porcelain started to chip or break at 507.28(${\pm}62.82$)kgf and the metal framework did not break until the maximum load level of 800kgf which was set in the testing instrument of this study. However, among all-ceramic restoration test groups, Everest(EV) group showed a peeling off or breakage of the porcelain from 365.64(${\pm}64.96$)kgf and the core was broken at 491.77(${\pm}55.62$)kgf. Those values of Zirkonzahn(ZR) were 431.03(${\pm}58.47$)kgf and 602.74(${\pm}48.44$)kgf, respectively. The break strength of the porcelain of PFM(PM) group was significantly higher than that of EV (p<0.05) group and there was no significant difference when comparing to that of ZR (p>0.05). ZR group showed higher break strength than that of EV group however there was no significant difference (p>0.05). The break strength of cores were in the increasing order of EV < ZR < PM (p<0.05). Conclusion: We could find that even though the PM group fractured at much higher value than all-ceramic cores, the breakage values of the porcelain of PM group with crack formation or delamination, which will be regarded as clinical failure, was significantly higher than that of EV group and not significantly higher than that of ZR group at p-values of 0.05. The break strength of ZR group was higher than that of EV group at an insignificant level(p>0.05).

• Journal of the Korean Electrochemical Society
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• v.5 no.3
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• pp.125-130
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• 2002

An attempt was made for the application of porous reticular metal to a heat dissipation material in semiconductor process. For this aim, the electrodeposition of Fe/Ni alloy on the porous reticular Cu has been performed to minimize the thermal expansion mismatch between Cu skeleton and electronic chip. Preliminary tests for the electrodeposition of Fe/Ni alloy layer were conducted by using standard Hull Cell to examine the effect of current density on the composition of alloy layer. It seemed that mass transfer affected significantly the composition of Fe/Ni layer due to anomalous codeposition in the electrodeposition of Fe/Ni alloy. A paddle type stirring bath, which was employed to control the mass transfer of electrolyte in the work, was found to allow the electrodeposition Fe/Ni with a precise composition. result showed that the thermal expansion of Fe/Ni alloy layer was much lower than that of pure copper. From the tests of heat dissipation by using the apparatus designed in the work the heat dissipation material fabricated in the work showed the excellent heat dissipation capacity, namely, more than two times as compared to that of pure copper plate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.750-755
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• 2003

This paper proposes a new three-line balun. The equivalent circuit of the proposed three-line balun is presented, and impedance matrix［Z］of the equivalent circuit is derived from the relationship between the current and voltage at each port. The design equation for a given set of balun impedance at input and output ports is presented using［S］parameters, which is transferred fom impedance matrix,［Z］. To demonstrate the feasibility and validity of design equation, multi-layer ceramic(MLC) chip balun operated in the 2.4 GHz ISM band frequency is designed and fabricated by the use of the low temperature co-fired ceramic(LTCC) technology. By employing both the proposed new three-line balun equivalent circuit and multi-layer configuration provided by LTCC technology, the 2012 size MLC balun is realized. Measured results of the multi-layer LTCC three-line balun match well with the full-wave electromagnetic simulation results, and measured in band-phase and amplitude balances over a wide bandwidth are excellent. This proposed balun is very easily applicable to multi-layer structure using LTCC as shown in the paper, and also can be realized with microstrip lines on PCB. This distinctive performance is very favorable for wireless communication systems such as wireless LAN(Local Area Network) and Bluetooth applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.5
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• pp.445-453
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• 2016

This paper presents the implementation and design of the 1T-1R wireless HD video streaming systems over 28 GHz mmWave frequency using 3GPP LTE-TDD standard on NI USRP RIO SDR platform. The baseband of the system uses USRP RIO that are stored in Xilinx Kintex-7 chip to implement LTE-TDD transceiver modem, the signal that are transceived from USRP RIO up or down converts to 28 GHz by using self-designed 28 GHz RF transceiver modules and it is finally communicated HD video data through self-designed $4{\times}8$ sub array antennas. It is that communication method between USRP RIO and Host PC use PCI express ${\times}4$ to minimize delay of data to transmit and receive. The implemented system show high error vector magnitude performance above 25.85 dBc and to transceive HD video in experiment environment anywhere.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.