• Journal of the Korean Arthroscopy Society
• /
• v.3 no.1
• /
• pp.40-43
• /
• 1999

Arthroscopic anterior cruciate ligament(ACL) reconstruction using four-strand hamstring tendon with looping around transfixing screw in femoral tunnel requires osteointegration between the grafted tendon and bone for stability of the knee. Authors have experienced a histologic finding of osteointegration between the grafted autogenous hamstring tendon and bone in femoral tunnel after arthroscopic ACL reconstruction. A patient received arthroscopic ACL reconstruction with autogenous four strand hamstring tendon for the ACL injury. Traumatic re-rupture of mid-substance of ACL graft was developed at thirteenth week after operation. During the procedures of arthroscopic revision at fifteenth week after initial ACL reconstruction, biopsy was performed at the site of interface between grafted tendon and bone in femoral tunnel. Integration between the grafted tendon and bone was evident by demonstrating the continuity of collagen fiber between bond and tendon. This histologic finding and the low incidence of early graft failure suggest that free tendon autograft attached to bone by looping around a transfixing screw in femoral tunnel undergoes adequate osteointegration between 12 and 15 weeks after surgery and authors thought that insertion of bone chip into the femoral tunnel would accelerate osteointegration procedure.

• IMMUNE NETWORK
• /
• v.5 no.4
• /
• pp.205-214
• /
• 2005

Background: We examined global gene expression profiles of peripheral blood mononuclear cells (PBMCs) in patients with ulcerative colitis (DC), and tested whether the identified genes with the altered expression might be associated with susceptibility to UC. Methods: PBMCs from 8 UC and 8 normal healthy (NH) volunteers were collected, and total RNAs were subjected to the human 8.0K cDNA chip for the micro array analysis. Real time-PCR (RT-PCR) was performed to verify the results of micro array. One hundred forty UC patients and 300 NH controls were recruited for single nucleotide polymorphism (SNP) analysis. Results: Twenty-five immune function-related genes with over 2-fold expression were identified. Of these genes, two chemokines, namely, CXCL1 and CCL20, were selected because of their potential importance in the evocation of host innate and adaptive immunity. Four SNPs were identified in the promoter and coding regions of CXCL1, while there was no significant difference between all patients with UC and controls in their polymorphisms, except minor association at g.57A>G (rs2071425, p=0.02). On the other hand, among three novel and one known SNPs identified in the promoter region of CCL20, g. -1,706 G>A (p=0.000000055), g. -1,458 G>A (p=0.0048), and g. -962C>A (p=0.0006) were found to be significantly associated with the susceptibility of Uc. Conclusion: Altered gene expression in mononuclear cells may contribute to IBD pathogenesis. Although the findings need to be confirmed in other populations with larger numbers of patients, the current results demonstrated that polymorphisms in the promoter region of CCL20 are positively associated with the development of Uc.

• Journal of the Korea Society of Computer and Information
• /
• v.19 no.4
• /
• pp.1-8
• /
• 2014

As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.

• Journal of Digital Convergence
• /
• v.11 no.4
• /
• pp.221-227
• /
• 2013

RFID is an automatic identification technology that can control a range of information via IC chips and radio communication. Also known as electronic tags, smart tags or electronic labels, RFID technology enables embedding the overall process from production to sales in an ultra-small IC chip and tracking down such information using radio frequencies. Currently, RFID-based application and development is in progress in such fields as health care, national defense, logistics and security. RFID structure consists of a reader that reads tag information, a tag that provides information and the database that manages data. Yet, the wireless section between the reader and the tag is vulnerable to security issues. To sort out the vulnerability, studies on security protocols have been conducted actively. However, due to difficulties in implementation, most suggestions are concerned with theorem proving, which is prone to vulnerability found by other investigators later on, ending up in many troubles with applicability in practice. To experimentally test the security of the protocol proposed here, the formal verification tool, CasperFDR was used. To sum up, the proposed protocol was found to be secure against diverse attacks. That is, the proposed protocol meets the safety standard against new types of attacks and ensures security when applied to real tags in the future.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.5
• /
• pp.27-37
• /
• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.34-44
• /
• 2006

A system-on-a-chip (SoC) design uses pre-verified IP hardware blocks in order to reduce design time. We need interface circuits to connect IPs with different protocols. In SoC design we should design interface circuits frequently and these tasks are somewhat time-consuming and error-prone. So it is necessary to generate the interface circuits automatically. Several studies have been made on generating interface circuits only from the communication protocols of IPs. With existing approaches, it is not easy to generate interface circuits connecting two IPs only from communication protocols: connection between IP with address and W without address, connection between IP with only one port to transfer address/data and IP with different ports for address and data connection between IP that transfer address and data together and IP that transfer only one address with a number of data in a burst. No consideration of various characteristics of IPs and no changed algorithm are responsible for it. In order to solve this problem, the proposed approach categorizes communication protocols of IPs, and takes characteristics matching of IPs into account during the interface synthesis. In experiments, we show that we could correctly generate and verify interface circuits for IPs with different characteristics.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.46 no.3
• /
• pp.1-8
• /
• 2009

DS-CDMA system has very low bandwidth efficiency, hence it is difficult to maintain high spreading gain for high speed data transmission. Offset stacked spreading CDMA(OSS-CDMA) is a transmission scheme where spreading codes with chip offsets are overlapped, then transmitted. This kind of system requires a code set that guarantees orthogonality between codes in the set of any cjip offset. An orthogonal complementary code set has a property that the crosscorrelation function between codes in the group is zero for all shifts, hence it can be used for an OSS-CDMA system. In an OCC-OSS CDMA system each user is assigned an orthogonal complementary code group. User data bit is spread by the given codes and overlapped, and the code sequences are transmitted with multicarrier. However, the offset stacked spread sequences are multilevel, and the number of symbol levels is increases as the spreading efficiency is increased. When the OSS sequence is transmitted with MPSK mapping, the signal constellation becomes dense, and the system is easily affected by channel impairments. In this paper, we propose a level clipping scheme on OSS sequence before MPSK modulated. Simulations have been carried out to investigate the BER performance of the OCC-OSS CDMA system in AWGN environment. The results show that proposed scheme outperform the scheme without level clipping.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.12
• /
• pp.75-82
• /
• 2010

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.1
• /
• pp.148-156
• /
• 2013

This paper suggests a multi-level and multi-output SMPS based on a shared digital logic controller through independently operating in each dedicated time periods. Although the shared architecture can be devised with small area and high efficiency, it has critical drawbacks that real-time control of each DPWM generators are impossible and its output voltage can be unstable. To solve these problems, a real-time current compensation scheme is proposed as a solution. A current consumption of the core block and entire block with four driver buffers was simulated about 4.9mA and 30mA at 10MHz switching frequency and 100MHz core operating frequency. Output voltage ripple was 11 mV at 3.3V output voltage. Over/undershoot voltage was 10mV/19.6mV at 3.3V output voltage. The noise performance was simulated at 800mA and 100KHz load regulation. Core circuit can be implemented small size in $700{\mu}m{\times}800{\mu}m$ area. For the verification of proposed circuit, the simulations were carried out with Dong-bu Hitek BCD $0.35{\mu}m$ technology.

• Journal of the Microelectronics and Packaging Society
• /
• v.22 no.2
• /
• pp.47-53
• /
• 2015

The effects of electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) surface finishes on the in-situ intermetallics reaction and the electromigration (EM) reliability of Sn-3.0Ag-0.5Cu (SAC305) solder bump were systematically investigated. After as-bonded, $(Cu,Ni)_6Sn_5$ intermetallic compound (IMC) was formed at the interface of the ENIG surface finish at solder top side, while at the OSP surface finish at solder bottom side,$ Cu_6Sn_5$ and $Cu_3Sn$ IMCs were formed. Mean time to failure on SAC305 solder bump at $130^{\circ}C$ with a current density of $5.0{\times}10^3A/cm^2$ was 78.7 hrs. EM open failure was observed at bottom OSP surface finish by fast consumption of Cu atoms when electrons flow from bottom Cu substrate to solder. In-situ scanning electron microscope analysis showed that IMC growth rate of ENIG surface finish was much lower than that of the OSP surface finish. Therefore, EM reliability of ENIG surface finish was higher than that of OSP surface finish due to its superior barrier stability to IMC reaction.