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Design of a step-up DC-DC Converter using a 0.18 um CMOS Process (0.18 um CMOS 공정을 이용한 승압형 DC-DC 컨버터 설계)

  • Lee, Ja-kyeong;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.6
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    • pp.715-720
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    • 2016
  • This paper proposes a PWM (Pulse Width Modulation) voltage mode DC-DC step-up converter for portable devices. The converter, which is operated with a 1 MHz switching frequency, is capable of reducing the mounting area of passive devices, such as inductor and capacitor, and is suitable for compact mobile products. This step-up converter consists of a power stage and a control block. The circuit elements of the power stage are an inductor, output capacitor, MOS transistors Meanwhile, control block consist of OPAMP (operational amplifier), BGR (band gap reference), soft-start, hysteresis comparator, and non-overlap driver and some protection circuits (OVP, TSD, UVLO). The hysteresis comparator and non-overlapping drivers reduce the output ripple and the effects of noise to improve safety. The proposed step-up converter was designed and verified in Magnachip/Hynix 0.18um 1-poly, 6-metal CMOS process technology. The output voltage was 5 V with a 3.3 V input voltage, output current of 100 mA, output ripple less than 1% of the output voltage, and a switching frequency of 1 MHz. These designed DC-DC step-up converters could be applied to the Personal Digital Assistants(PDA), cellular Phones, Laptop Computer, etc.

Design and Analysis of a 12 V PWM Boost DC-DC Converter for Smart Device Applications (스마트기기를 위한 12 V 승압형 PWM DC-DC 변환기 설계 및 특성해석)

  • Na, Jae-Hun;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.6
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    • pp.239-245
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    • 2016
  • In this study, a 12 V PWM boost converter was designed with the optimal values of the external components of the power stage was well as the compensation stage for smart electronic applications powered by a battery device. The 12 V boost PWM converter consisted of several passive elements, such as a resistor, inductor and capacitor with a diode, power MOS switch and control IC chip for the control PWM signal. The devices of the power stage and compensation stage were designed to maintain stable operation under a range of load conditions as well as achieving the highest power efficiency. The results of this study were first verified by a simulation in SPICE from calculations of the values of major external elements comprising the converter. The design was also implemented on the prototype PCBboard using commercial IC LM3481 from Texas Instruments, which has a nominal output voltage of 12 V. The output voltage, ripple voltage, and load regulation with the line regulation were measured using a digital oscilloscope, DMM tester, and DC power supply. By configuring the converter under the same conditions as in the circuit simulation, the experimental results matched the simulation results.

Exploiting cDNA Microarray-Based Approach Combined with RT-PCR Analysis to Monitor the Radiation Effect: Antioxidant Gene Response of ex vivo Irradiated Human Peripheral Blood Lymphocyte

  • Sung, Myung-Hui;Jun, Hyun-Jung;Hwang, Seung-Yong;Hwang, Jae-Hoon;Park, Jong-Hoon;Han, Mi-Young;Lee, U-Youn;Park, Eun-Mi;Park, Young-Mee
    • Environmental Mutagens and Carcinogens
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    • v.22 no.3
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    • pp.142-148
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    • 2002
  • Although ionizing radiation (IR) has been used to treat the various human cancers, IR is cytotoxic not only to cancer cells but to the adjacent normal tissue. Since normal tissue complications are the limiting factor of cancer radiotherapy, one of the major concerns of IR therapy is to maximize the cancer cell killing and to minimize the toxic side effects on the adjacent normal tissue. As an attempt to develop a method to monitor the degree of radiation exposure to normal tissues during radiotherapy, we investigated the transcriptional responses of human peripheral blood lymphocytes (PBL) following IR using cDNA microarray chip containing 1,221 (1.2 K) known genes. Since conventional radiotherapy is delivered at about 24 h intervals at 180 to 300 cGy/day, we analyzed the transcriptional responses ex-vivo irradiated human PBL at 200 cGy for 24 h-period. We observed and report on 1) a group of genes transiently induced early after IR at 2 h, 2) of genes induced after IR at 6 h, 3) of genes induced after IR at 24 h and on 4) a group of genes whose expression patters were not changed after IR. Since Biological consequences of IR involve generation of various reactive oxygen species (ROS) and thus oxidative stress induced by the ROS is known to damage normal tissues during radiotherapy, we further tested the temporal expression profiles of genes involved in ROS modulation by RT-PCR. Specific changes of 6 antioxidant genes were identified in irradiated PBL among 9 genes tested. Our results suggest the potential of monitoring post-radiotherapy changes in temporal expression profiles of a specific set of genes as a measure of radiation effects on normal tissues. This type of approach should yield more useful information when validated in in vivo irradiated PBL from the cancer patients.

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Measurements of Lattice Strain in MOCVD-GaN Thin Film Grown on a Sapphire Substrate Treated by Reactive Ion Beam (활성화 이온빔 처리된 Sapphire기판 위에 성장시킨 MOCVD-GaN 박막의 격자변형량 측정)

  • Kim, Hyun-Jung;Kim, Gyeung-Ho
    • Applied Microscopy
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    • v.30 no.4
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    • pp.337-345
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    • 2000
  • Introduction of the buffer layer and the nitridation of a sapphire substrate were one of the most general methods employed for the reduction of lattice defects in GaN thin films Brown on sapphire by MOCVD. In an effort to improve the initial nucleation and growth condition of the GaN, reactive ion beam (RIB) of nitrogen treatment of the sapphire surface has been attempted. The 10 nm thick, amorphous $AlO_xN_y$ layer was formed by RIB and was partially crystallized alter the main growth of GaN at high temperature, leaving isolated amorphous regions at the interface. The beneficial effect of amorphous layer at interface in relieving the thermal stress between substrate and GaN film was examined by measuring the lattice strain value of the GaN film grown with and without the RIB treatment. Higher order Laue zone pattern (HOLZ) of $[\bar{2}201]$ zone axis was compared with simulated patterns and lattice strain was estimated It was confirmed that the great reduction of thermal strain was achieved by RIB process and the amount of thermal stress was 6 times higher in the GaN film grown by conventional method without the RIB treatment.

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A Temperature- and Supply-Insensitive 1Gb/s CMOS Open-Drain Output Driver for High-Bandwidth DRAMs (High-Bandwidth DRAM용 온도 및 전원 전압에 둔감한 1Gb/s CMOS Open-Drain 출력 구동 회로)

  • Kim, Young-Hee;Sohn, Young-Soo;Park, Hong-Jung;Wee, Jae-Kyung;Choi, Jin-Hyeok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.8
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    • pp.54-61
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    • 2001
  • A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

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Studies on the Quality of Processing Potatoes grown at Different Locations (裁培地域에 따른 加工用 감자의 品質에 關한 硏究)

  • 양성지
    • Korean Journal of Plant Resources
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    • v.10 no.1
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    • pp.30-38
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    • 1997
  • Influence of different cultivated areas on the processing-grade tuber yield, specific gravity, reducing sugar content and tuber qualities of five promising varieties was studied to get the basic information for selecting potato varieties with good processing quality under the different cultivated conditions on Korea. The average total tuber yields of 5 tested varieties at the 2nd harvest time was 3,.051kg/10a in Daekwallyoung. The processing-grade tuber yield of the late-maturing variety of Gemchip was over 3.2 tons per 10a, whereas that of late-maturing variety, NS1 was 2.8 tons per 10a. The dry matter content of the tubers produced from Daekwallyoung was the highest, followed by the order of Bosung, atlantic was the highest in dry matter content, followed by the order of NS1, NS2, Superior and Gemchip. Degrees of change in glucose content as affected by change of cultivated areas were different among varieties. Atlantic and NS1 showed less change of glucose content as compared with other varieties.

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Spalling of Intermetallic Compound during the Reaction between Electroless Ni(P) and Lead-free Solders (무전해 Ni(P)과 무연솔더와의 반응 중 금속간화합물의 spalling 현상에 관한 연구)

  • Sohn Yoon-Chul;Yu Jin;Kang S. K.;Shih D. Y,;Lee Taek-Yeong
    • Journal of the Microelectronics and Packaging Society
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    • v.11 no.3 s.32
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    • pp.37-45
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    • 2004
  • Electroless Ni(P) has been widely used for under bump metallization (UBM) of flip chip and surface finish layer in microelectronic packaging because of its excellent solderability, corrosion resistance, uniformity, selective deposition without photo-lithography, and also good diffusion barrier. However, the brittle fracture at solder joints and the spatting of intermetallic compound (IMC) associated with electroless Ni(P) are critical issues for its successful applications. In the present study, the mechanism of IMC spatting and microstructure change of the Ni(P) film were investigated with varying P content in the Ni(P) film (4.6,9, and $13 wt.\%$P). A reaction between Sn penetrated through the channels among $Ni_3Sn_4$ IMCs and the P-rich layer ($Ni_3P$) of the Ni(P) film formed a $Ni_3SnP$ layer. Thickening of the $Ni_3SnP$ layer led to $Ni_3Sn_4$ spatting. After $Ni_3Sn_4$ spatting, the Ni(P) film directly contacted the molten solder and the $Ni_3P$ phase further transformed into a $Ni_2P$ phase. During the crystallization process, some cracks formed in the Ni(P) film to release tensile stress accumulated from volume shrinkage of the film.

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Fabrication Method of High-density and High-uniformity Solder Bump without Copper Cross-contamination in Si-LSI Laboratory (실리콘 실험실에 구리 오염을 방지 할 수 있는 고밀도/고균일의 Solder Bump 형성방법)

  • 김성진;주철원;박성수;백규하;이희태;송민규
    • Journal of the Microelectronics and Packaging Society
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    • v.7 no.4
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    • pp.23-29
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    • 2000
  • We demonstrate the fabrication method of high-density and high-quality solder bump solving a copper (Cu) cross-contamination in Si-LSI laboratory. The Cu cross-contamination is solved by separating solder-bump process by two steps. Former is via-formation process excluding Cu/Ti under ball metallurgy (UBM) layer sputtering in Si-LSI laboratory. Latter is electroplating process including Ti-adhesion and Cu-seed layers sputtering out of Si-LSI laboratory. Thick photoresist (PR) is achieved by a multiple coating method. After TiW/Al-electrode sputtering for electroplating and via formation in Si-LSI laboratory, Cu/Ti UBM layer is sputtered on sample. The Cu-seed layer on the PR is etched during Cu-electroplating with low-electroplating rate due to a difference in resistance of UBM layer between via bottom and PR. Therefore Cu-buffer layer can be electroplated selectively at the via bottom. After etching the Ti-adhesion layer on the PR, Sn/Pb solder layer with a composition of 60/40 is electroplated using a tin-lead electroplating bath with a metal stoichiometry of 60/40 (weight percent ratio). Scanning electron microscope image shows that the fabricated solder bump is high-uniformity and high-quality as well as symmetric mushroom shape. The solder bumps with even 40/60 $\mu\textrm{m}$ in diameter/pitch do not touch during electroplating and reflow procedures. The solder-bump process of high-uniformity and high-density with the Cu cross-contamination free in Si-LSI laboratory will be effective for electronic microwave application.

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Luminescence Characteristics of Mg2+·Ba2+ Co-Doped Sr2SiO4:Eu Yellow Phosphor for Light Emitting Diodes (LED용Mg2+·Ba2+Co-Doped Sr2SiO4:Eu 노란색 형광체의 발광특성)

  • Choi, Kyoung-Jae;Jee, Soon-Duk;Kim, Chang-Hae;Lee, Sang-Hyuk;Kim, Ho-Kun
    • Journal of the Korean Ceramic Society
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    • v.44 no.3 s.298
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    • pp.147-151
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    • 2007
  • An improvement for the efficiency of the $Sr_{2}SiO_{4}:Eu$ yellow phosphor under the $450{\sim}470\;nm$ excitation range have been achieved by adding the co-doping element ($Mg^{2+}\;and\;Ba^{2+}$) in the host. White LEDs were fabricated through an integration of an blue (InGaN) chip (${\lambda}_{cm}=450\;nm$) and a blend of two phosphors ($Mg^{2+},\;Ba^{2+}\;co-doped\;Sr_{2}SiO_{4}:Eu$ yellow phosphor+CaS:Eu red phosphor) in a single package. The InGaN-based two phosphor blends ($Mg^{2+},\;Ba^{2+}\;co-doped\;Sr_{2}SiO_{4}:Eu$ yellow phosphor+CaS:Eu red phosphor) LEDs showed three bands at 450 nm, 550 nm and 640 nm, respectively. The 450 nm emission band was due to a radiative recombination from an InGaN active layer. This 450 nm emission was used as an optical transition of the $Mg^{2+},\;Ba^{2+}\;co-doped\;Sr_{2}SiO_{4}:Eu$ yellow phosphor+CaS:Eu red phosphor. As a consequence of a preparation of white LEDs using the $Mg^{2+},\;Ba^{2+}\;co-doped\;Sr_{2}SiO_{4}:Eu$ yellow phosphor+CaS:Eu red phosphor yellow phosphor and CaS:Eu red phosphor, the highest luminescence efficiency was obtained at the 0.03 mol $Ba^{2+}$ concentration. At this time, the white LEDs showed the CCT (5300 K), CRI (89.9) and luminous efficacy (17.34 lm/W).

Evaluation of Field Applicability of Pavement Materials Using Wood Chips (목재칩을 활용한 포장재의 현장 적용성 평가)

  • Lee, Jundae;Bang, Sungtak;Bae, Wooseok
    • Journal of the Korean GEO-environmental Society
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    • v.16 no.11
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    • pp.13-19
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    • 2015
  • Construction materials using soil which is the most common material around us have many advantages, but their long-term durability and sensation of walking as pavements have problems. Therefore, they are used after compaction or mixed with various hardening agents such as lime and cement for strength enhancement. However, studies on the behavior of pavement materials mixed with environment-friendly hardening agents or admixtures to improve walking property are still insufficient. In this study, therefore, in order to evaluate the appropriate mixing ratio and field application characteristics of pavement materials using mixed soils with environment-friendly hardening agents and natural materials such as wood chips, mechanical tests were performed to evaluate the rational mixing ratios and the ball test was performed as an elasticity test to evaluate the field applicability. The results suggest that the content of wood chips should be selected at 1.5% or lower according to the purpose of the structure, and the hardening agent at 10~15%. The evaluation results for GB/SB coefficient ratio which indicates the walking property show that the appropriate mixing ratio of the hardening agent in terms of the sensation of walking is 15% of lower, but different mixing ratios should be chosen according to the proportion of wood chips.