• 한국전기전자재료학회논문지
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• 제28권10호
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• pp.676-681
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• 2015

Recently many studies being carried out to increase the light efficiency of LED. The external quantum efficiency of LED, generally the light efficiency, is determined by the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency of LED was already reached to more than 90%, but the light extraction efficiency is still insufficient compared with the internal quantum efficiency because the total internal reflection is generated in the interface between the LED chip and air. Thus, we studied about flip chip LED with PSS and performed the optical simulation which find more optimized PSS for flip chip LED to increase the light extraction efficiency. Decreasing of the total internal reflection and effect of diffused reflection according to PSS improved the light extraction efficiency. To get more higher the efficiency, we simulated flip chip with PSS that the parameters are arrangement, edge spacing, radius, height and shape of PSS.

• 대한임상검사과학회지
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• 제43권1호
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• pp.26-31
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• 2011

The genotypes of Human Papilloma Virus (HPV) are important in the carcinogenesis of uterine cervical cancer. Diagnosis of uterine cervical cancer screening has been executed using Papanicolau method (Pap) and HPV DNA Chip method. We researched the interrelation of HPV DNA genotypes in single and multiple infections and analyzed the results of Pap and HPV DNA Chip tests at Gunsan Medical Center (GMC). The correlation analysis was surveyed on collected results from 599 patients who have been tested with both Pap and HPV DNA chip tests from November 2004 to May 2010 at GMC. The inconsistency between Pap and HPV DNA Chip tests was 41.1%. The HPV DNA Chip genotype related with high risk cases were type 16 (13.5%), type 52 (10.5%), type 58 (10.1%), and type 18 (3.4%). Those related with low risk cases were type 70 (8.9%), type 6 (1.7%), type 40 (1.2%), type 11 (1.3%), and other types (14.3%). Among the 195 cases of HPV positive status, 161 cases were associated with single infection; 108 (67.1%) cases were related with high risk genotype; 19 (11.8%) cases were low risk genotype; 31 (21.1%) cases were related with other types. 29 cases were associated with double infections; 23 (79.3%) cases were high risks; 5 (17.2%) cases were mixed high and low risks; 1 (3.5%) case was low risk.

• 한국전기전자재료학회논문지
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• 제32권1호
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• pp.47-52
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• 2019

Micro-LEDs show lower efficiencies compared to general LEDs having large areas. Simulations were carried out using ray-tracing software to investigate the change in light extraction efficiency and light distribution according to chip-size of blue flip-chip micro-LEDs (FC ${\mu}-LEDs$). After fixing the height of the square FC ${\mu}-LED$ chip at $158{\mu}m$, the length of one side was varied, with dimensions of 2, 5, 10, 30, 50, 100, 300, and $500{\mu}m$. The highest light-extraction efficiency was obtained at $10{\mu}m$, beyond which the efficiency decreased as the chip-size increased. The chip size-dependence of the FC ${\mu}-LEDs$ both without the patterned sapphire substrate, as well as vertical FC ${\mu}-LEDs$, were analyzed.

• 한국기계가공학회지
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• 제20권1호
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• pp.103-109
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• 2021

Fine chips generated by machining have an impact on machine failure and quality of machined products, it is necessary to remove the chips, so the microchip collection and removal device by rotating conveyor belt with neodymium permanent magnets was developed. In this research, to solve the problem for reducing the existing microchips in the tank, a micro-chip removal device by rotating conveyor belt with neodymium permanent magnets developed. In the development of micro-chip removal device, 3D CATIA modeling was used, and the flow analysis and the electromagnetic force analysis were performed with COMSOL Multiphysics program. To evaluate the performance of the prototypes produced, design of experiments (DOE) is used to obtain the effect of neodymium conveyor movement speed on chip removal for the ANOVA analysis of recovered powders. An experiment was conducted to investigate the effect of the conveyor feed rate on the chip removal performance in detail. As a result of the experiment, it was confirmed that the slower the feeding speed of the fine chip removing device, the more efficient the chip removal.

• 마이크로전자및패키징학회지
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• 제15권3호
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• pp.53-58
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• 2008

본 연구에서는 상용화된 2.4 GHz 영역대에서 사용되어지는 WiFi용 DPDT(Double Pole Double throw) switch 칩을 laser 비아 가공과 도금 공정을 이용하여 폴리머 기판내에 내장시켜 그 특성을 분석하였으며 통상적으로 실장되는 wire 본딩방식으로 패키징된 기판과 특성차이를 분석 비교하였다. 폴리머는 FR4기판과 아지노 모토사의 ABF(Ajinomoto build up film)를 이용하여 패턴도금법으로 회로를 형성하였다. ABF공정의 최적화를 위해 폴리머의 경화정토를 DSC (Differenntial Scanning Calorimetry) 및 SEM (Scanning Electron microscope)으로 분석하여 경화도에 따라 도금된 구리패턴과의 접착력을 평가하였다. ABF의 가경화도가 $80\sim90%$일 경우 구리층과 최적의 접착강도를 보였으며 진공 열압착공정을 통해 기공(void)없이 칩을 내장할 수 있었다. 내장된 기관과 와이어 본딩된 기판의 측정은 S 파라미터를 이용하여 삽입손실과 반사손실을 비교 분석하였으며 그 결과 삽입손실은 두 경우 유사하게 나타났지만 반사손실의 경우 칩이 내장된 경우 6 GHz 까지 -25 dB 이하로 안정적으로 나오는 것을 확인할 수 있었다.

• 마이크로전자및패키징학회지
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• 제16권3호
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• pp.67-73
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• 2009

Cu pillar 범프를 사용한 플립칩 접속부는 솔더범프 접속부에 비해 칩과 기판사이의 거리를 감소시키지 않으면서 미세피치 접속이 가능하기 때문에, 특히 기생 캐패시턴스를 억제하기 위해 칩과 기판사이의 큰 거리가 요구되는 RF 패키지에서 유용한 칩 접속공정이다. 본 논문에서는 칩에는 Cu pillar 범프, 기판에는 Sn 범프를 전기도금하고 이들을 플립칩 본딩하여 Cu pillar 범프 접속부를 형성 한 후, Sn 전기도금 범프의 높이에 따른 Cu pillar 범프 접속부의 접속저항과 칩 전단하중을 측정하였다. 전기도금한 Sn 범프의 높이를 5 ${\mu}m$에서 30 ${\mu}m$로 증가시킴에 따라 Cu pillar 범프 접속부의 접속저항이 31.7 $m{\Omega}$에서 13.8 $m{\Omega}$로 향상되었으며, 칩 전단하중이 3.8N에서 6.8N으로 증가하였다. 반면에 접속부의 종횡비는 1.3에서 0.9로 저하하였으며, 접속부의 종횡비, 접속저항 및 칩 전단하중의 변화거동으로부터 Sn 전기도금 범프의 최적 높이는 20 ${\mu}m$로 판단되었다.

• KIEE International Transactions on Electrophysics and Applications
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• 제4C권4호
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• pp.133-136
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• 2004

This research aims to develop a DNA chip array without an indicator. We fabricated a microelectrode array through photolithography technology. Several DNA probes were immobilized on an electrode. Then, target DNA was hybridized and measured electrochemically. Cyclic-voltammograms (CVs) showed a difference between the DNA probe and mismatched DNA in an anodic peak. This indicator-free DNA chip resulted in a sequence-specific detection of the target DNA.

• 전자통신동향분석
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• 제4권4호
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• pp.108-134
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• 1989

본 고는 현재 공중회선망을 이용한 PC 통신에 필수장비인 모뎀을 구성하는 2,400bps Modem Chip Set을 비교하였다. 현재 널리 사용되는 Modem Chip Set들은 주로 2-3개 Chip으로 구성되며, 이것들을 사용하여 완전한 2,400bps Modem을 구성할 수 있다. 이러한 모뎀용 IC는 PC통신뿐만 아니라 휴대용 Terminal, 차량추적시스팀, 휴대용 전화기, 각종 원격검침계량기 등에서와 같이 그 사용범위가 다양화되고 있는 추세이다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 2nd Korea-Japan Advanceed Semiconductor Packaging Technology Seminar
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• pp.7-38
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• 2000

Performance, reliability, form factor drive flip chip use. BGAs and CSPs will provide stepping stone to FC DCA .Growing vendor infrastructure - Low cost, high density organic substrates -New generations of fluxes and underfills .Adhesives flip chip technology as a low cost flip chip alternatives -Low cost Au stud or Electroless Ni bumps -Reliable thermal cycling and electrical performance.

• 전자공학회논문지A
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• 제31A권12호
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• pp.122-134
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• 1994

Design of a heuristic algorithm for high level synthesis of multichip architecture is presented in this paper. Considering the design constraints: individual chip area, I/O pin counts, chip-to-chip interconnection counts, interchip communication delay, and chip latecy, the proposed system automatically generates pipelined multichip architectures from behavioral descriptions. For efficient mulichip synthesis, a new methodology is proposed, which performs partitioning and schedulting of SFG into multichip architectures simultaneously. Experimental results for several benchmark programs show that the systems can be used for designing multichip hardware efficiently.