• Journal of Sensor Science and Technology
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• v.25 no.2
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• pp.143-147
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• 2016

Characteristics of the conventional gold (Au) surface plasmon resonance (SPR) chip, bi-metallic(Au/silver (Ag)) SPR chip, and tri-metallic(Au/Ag/Au) SPR chip were investigated and compared in the intensity measurement mode for the enhancement of SPR image sensor reactivity. Reflectance curves of the Au, bi- and tri-metallic SPR chips were acquired in phosphate-buffered saline (PBS) solution and were compared. The line width of the reflectance curve of the bi-metallic chip was the narrowest among the three different types of the chips. Also, the tangential slope of the bi-metallic chip was steeper than those of the other chips. Various concentrations of bovine serum albumin (BSA) were utilized in the SPR experiment. As a result, among the above three chips reflectance variation value of the bi-metallic chip was the largest.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.1
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• pp.41-47
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• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.7
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• pp.328-334
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• 2002

The DNA chips are devices associating the specific recognition properties of two DNA single strands through hybridization process with the performances of the microtechnology. In the literature, the "Gene chip" or "DNA chip" terminology is employed in a wide way and includes macroarrays and microarrays. Standard definitions are not yet clearly exposed. Generally, the difference between macro and microarray concerns the number of active areas and their size, Macroarrays correspond to devices containing some tens spots of 500$\mu$m or larger in diameter. microarrays concern devices containing thousnads spots of size less than 500$\mu$m. The key technical parameters for evaluating microarray-manufacturing technologies include microarray density and design, biochemical composition and versatility, repreducibility, throughput, quality, cost and ease of prototyping. Here we report, a new method in which minute particles are arranged in a random fashion on a chip pattern using random fluidic self-assembly (RFSA) method by hydrophobic interaction. We intend to improve the stability of the particles at the time of arrangement by establishing a wall on the chip pattern, besides distinction of an individual particle is enabled by giving a tag structure. This study demonstrates the fabrication of a chip pattern, immobilization of DNA to the particles and arrangement of the minute particle groups on the chip pattern by hydrophobic interaction.ophobic interaction.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• Resources Recycling
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• v.6 no.4
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• pp.24-30
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• 1997

The recent trend of recycle of mold scrap is to make high quality secondary ingot which can be used as raw malerial undcr intensive control of scrap. In this study, recycle of aluminum chlp generated atter machinmg process of castings was performed by vortex melting melhod Vortex melting technique was adopted for chip mclting process. The condition far optimal vortcx depth was decided using water mndellng experiment varying the shape, location, rotating speed of stlircr and watcr levcl. Before melting, chips were preheated at room temperame, 200, 300, $ 400^{\circ}C$and then submerged in the mirldle of vortex. The lecovery rale depending on the temperature was examined. As a result vortex depth was influenccd only by shape and rotating speed of stirrer, and the hlghest recovery rate oI 97% was obta~nedw hcn the submerged chip was preheated at $300^{\circ}C.$

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.6
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• pp.175-181
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• 2013

The primary element of machining automation is to maximize the utilization of machine tools, which determines the output and lead-time. In particular, 95% of raw materials for wing ribs are cut into chips and 0.6 ton of chips are generated every hour from each machine tool. In order to verify the chip recycling system that controls the chips from the machines in five-axis FMS line, a simulation of the virtual model is constructed using the QUEST simulation program. The optimum speed of the chip conveyor and its operating conditions that directly affect the efficiency of the FMS line are presented including the chip conveyor speed, the maximum capacity of the hopper, and the number of chip compressors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1564-1573
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• 2007

Bulk of toner residual quantity detection return trip conglutinated in toner of using printer current is comparative big state by using PCB substrate, therefore is incongruent to use in light weight print miniaturized more. Return trip this development miniaturizes such as this by doing one chip competitive product develop chip has to be conglutinated compulsorily in toner used to printer announced since 2005 years. Therefore, demand of chip to be used in forward revival market may be thriving. Production of revival toner is impossible by chip conglutinated to printer to meaning that manage information of toner cut ridge that universal laser printer makers are used in printer and do customer service. In this paper, we develops chip conglutinated compulsorily to produce revival toner.

• Journal of the Korean Physical Society
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• v.73 no.9
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• pp.1346-1350
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• 2018

An electrode-evaporation technology on both the top and bottom sides of the bare vertical-type single chip separated from the traditional substrate by cooling, was developed for III-nitride vertical-type single chip LEDs with thick GaN epilayer. The post-process of the cooling step was followed by sorting the bare vertical-type single chip LEDs into the holes in a pocket-type shadow mask for deposition of the electrodes at the top and bottom sides of bare vertical-type single chip LEDs without the traditional substrate for electrode evaporation technology for vertical-type single chip LEDs. The variation in size of the hole between the designed shadow mask and the deposited electrodes owing to the use of the designed pocket-type shadow mask is investigated. Furthermore, the electrical and the optical properties of bare vertical-type single chip LEDs deposited with two different shapes of n-type electrodes using the pocket-type shadow mask are investigated to explore the possibility of the e-beam evaporation method.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.9
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• pp.1408-1414
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• 2004

The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF (anisotropic conductive film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue lift of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear hi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2$^{nd}$ DOE was conducted to obtain RSM equation far the choose 3 design parameter. The coefficient of determination ($R^2$) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430$\mu$m, and 78$\mu$m, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter should be controlled within 3% of average value.

• Asian Journal of Turfgrass Science
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• v.16 no.1
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• pp.19-30
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• 2002

This study was conducted to investigated the effects of rubber chips from used tires on sports turf ground as soil conditioner to improve soil physical properties. The release of heavy metal ions was detected to check the soil contamination by incorporation of recycled rubber chips with topsoil. The effects of the chips were also evaluated as topdressing material to improve surface resilience. The rate of rubber chips showed a positive relationship with soil temperature increasement. Incorporation of rubber chips increased soil temperature on surface at 2.5 cm-depth. The rates of rubber chip showed a negative relationship with ground cover rate of turfgrass in early growth season. However, after 20 weeks, treatment of 10% rubber chips at 2.5 cm-depth showed a prominent cover rate of 70% which was not significantly different with untreated control. Incorporation of rubber chips within topsoil seemed to reduce soil compaction, but the effects was not prominent on physical properties. Rubber chips did not affect chemical properties and heavy metal contamination to soil environment. Rubber chips improved resilience of the compacted ground surface as topdressing material, this effect was prominent when aerification practise was preceded.