• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.111-120
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• 2011

A two-dimensional analytical model for deriving the threshold voltage of a short channel fully depleted (FD) cylindrical/surrounding gate MOSFET (CGT/SGT) is suggested. By taking into account the lateral variation of the surface potential, introducing the natural length expression, and using the Bessel functions of the first and the second kinds of order zero, we can derive potentials in the gate oxide layer and the silicon core fully two-dimensionally. Making use of these potentials, the minimum surface potential can be obtained to derive the threshold voltage as a closed-form expression in terms of various device parameters and applied voltages. Obtained results can be used to explain the drain-induced threshold voltage roll-off of a CGT/SGT in a unified manner.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.458-466
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• 2012

A Dual metal gate stack cylindrical/ surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.

• 한국작물학회지
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• 제59권3호
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• pp.341-349
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• 2014

경실로 인해 다른 두과작물에 비해 포장 입묘가 불량한 팥의 포장출현율의 효과적인 예측 방법을 개발하기 위해 인위로 노화 정도를 조절한 종자에 대해 실험실에서 몇 가지 종자세 검사를 실시하여 포장출현력과 비교하였다. 얻어진 종자세 지표들에 대해 포장출현력과의 상관분석을 통해 예측을 위한 효율적인 지표들을 도출하였다. 팥에서 종자세가 높을 경우에는 표준발아검사에서의 종자활력률이 포장출현력 예측에 효과적이며, 약간 노화된 종자의 경우에는 저온발아검사(CGT)에서의 비정상묘율과 배축의 길이는 포장출현력과 높은 상관관계를 보였으며, 전기전도도와 CSVT에서의 활력률과 테트라졸리움 검사에서 종자세와 예측발아율은 포장출현력과 5% 수준에서 상관관계가 인정되었다. 종자세가 낮은 종자에서는 CSVT에서 불발아종자율이 포장출현력과 5% 수준에서 상관을 보였다. 포장출현력 예측에 효과적인 몇 가지 종자세지수를 이용하여 stepwise multiple regression 분석을 실시한 결과 테트라졸리움(TZ) 검사에서의 예측발아율은 결정계수($R^2$)가 0.820으로 포장출현력 예측에 가장 효과적인 검사방법임을 알 수 있었다. 표준발아검사(SGT)에서의 종자활력률, 저온발아검사(CGT)에서의 정상묘율과 건물중을 회귀방정식에 추가함에 따라 86.9% 까지 포장출현력 예측효율을 증가시킬 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.377-387
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• 2012

An intrinsic small signal equivalent circuit model of Cylindrical/Surrounded gate MOSFET is proposed. Admittance parameters of the device are extracted from circuit analysis and intrinsic circuit elements are presented in terms of real and imaginary parts of the admittance parameters. S parameters are then evaluated and justified with the simulated data extracted from 3D device simulation.