• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.113-114
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• 2018

ITER TF AC/DC Converter는 2Quadrant 동작하며 컨버터 변압기의 무부하 Tap chage position에 따라 출력 전압은 ${\pm}160V/68000A$, ${\pm}650V/68000A$ 2가지 출력 사양으로 동작한다. TF Local Controller는 2상한 동작과 변압기 Tap change 제어에서 높은 신뢰도를 요구 한다. 본 논문은 RTDS를 이용하여 TF 컨버터 제어기의 성능을 검증한 내용을 논의하고자 한다.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.103-107
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• 2021

In this paper, a capacitive water level sensor for boilers was developed. In order to accurately monitor the water level in a high-temperature boiler that generates a lot of precipitates, the occurrence of precipitates on the surface of the water level sensor should be small, and a sensor capable of measuring even if the sensor surface is somewhat contaminated is required. The capacitive water level sensor has a structure in which one of the two electrodes is insulated with Teflon coating, and the stainless steel package of the water level sensor is brought into contact with the water tank so that the entire water tank becomes another electrode of the water level sensor. A C-V converter that converts the capacitance change of the capacitive water level sensor into a voltage change was developed and integrated with the water level sensor to minimize noise. The performance of the developed capacitive water level sensor was evaluated through measurement.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.10-17
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• 1999

In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.13-19
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• 1999

This paper describes a design of an 8-bit 100KSPS 1mW CMOS A/D Converter. Using a novel systematic offset cancellation technique, we reduce the systematic offset voltage of operational amplifiers. Further, a new Gain amplifier is proposed. The proposed A/D Converter is fabricated with a $0.6{\mu}m$ single-poly triple-metal n-well CMOS technology. INL and DNL is within ${\pm}1LSB$, and SNR is about 43dB at the sampling frequency of 100KHz. The power consumption is $980{\mu}W$ at +3V power supply.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.707-710
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• 1998

This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a $0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is $20\muV/^{\circ}C,$ supply voltage dependency is $\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is $5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.902-904
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• 2005

The AC-DC converter, which has three-phase AC power as input and isolated DC power as output is used for the regulated DC power supply of the telecommunication power processing system for several kilowatt class applications. The conventional DC power supply for the telecommunication power system comprises a PWM rectifier with sine-wave shaping input current unity power factor and a DC/DC converter connected to the PWM converter, which obtains DC 48[V]. Since power passes through these two power stage converters, the conversion power loss is difficult to provide high efficiency. To resolve these problems, this paper presents a new PWM rectified as a 1-stage power conversion method. It simulation and experimental results as proved from a practical point of view that 92.1[%]of conversion efficiency and input current which can meet harmonics regulation of the Class-A in IEC61000-3-3 are achieved.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2462-2464
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• 2005

The AC-DC converter, which has three-phase AC power as input and isolated DC power as output is used for the regulated DC power supply of the telecommunication power processing system for several kilowatt class applications. The conventional DC power supply for the telecommunication power system comprises a PWM rectifier with sine-wave shaping input current unity power factor and a DC/DC converter connected to the PWM converter, which obtains DC 48[V]. Since power passes through these two power stage converters, the conversion power loss is difficult to provide high efficiency. To resolve these problems, this paper presents a new PWM rectified as a 1-stage power conversion method. It simulation and experimental results as proved from a Practical point of view that 92.1[%]of conversion efficiency and input current which can meet harmonics regulation of the Class-A in IEC61000-3-3 are achieved.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1820-1822
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• 2005

The AC-DC converter, which has three-phase AC power as input and isolated DC power as output is used for the regulated DC power supply of the telecommunication power processing system for several kilowatt class applications. The conventional DC power supply for the telecommunication power system comprises a PWM rectifier with sine-wave shaping input current unity power factor and a DC/DC converter connected to the PWM converter, which obtains DC 48[V]. Since power passes through these two power stage converters, the conversion power loss is difficult to provide high efficiency. To resolve these problems, this paper presents a new PWM rectified as a 1-stage power conversion method. It simulation and experimental results as proved from a practical point of view that 92.1[%]of conversion efficiency and input current which can meet harmonics regulation of the Class-A in IEC61000-3-3 are achieved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.378-384
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• 2013

In this paper, a CMOS temperature sensor is proposed to measure the internal temperature of a chip. The temperature sensor consists of a proportional-to-absolute-temperature (PTAT) circuit for a temperature sensing part and a 4-bit analog-to-digital converter (ADC) for a digital interface. The PTAT circuit with the compact area is designed by using a vertical PNP architecture in the CMOS process. To reduce sensitivity of temperature variation in the digital interface circuit of the proposed temperature sensor, a 4-bit successive approximation (SA) ADC using the minimum analog circuits is used. It uses a capacitor-based digital-to-analog converter and a time-domain comparator to minimize power consumption. The proposed temperature sensor was fabricated by using a $0.25{\mu}m$ 1-poly 6-metal CMOS process with a 2.5V supply, and its operating temperature range is from 50 to $150^{\circ}C$. The area and power consumption of the fabricated temperature sensor are $130{\times}390{\mu}m^2$ and $868{\mu}W$, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.4
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• pp.1797-1805
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• 2012

In this paper, Power LED(Light Emitting Diodes) is studied to driver as a new lighting system in the spotlight, replacing a large existing lighting system with fluorescent and incandescent lighting. To take advantage a variety of DC power as the boost DC-DC converter design specifications through the inductor L and capacitor C through PSPICE to calculate the best estimate of the value. Converter's switching frequency is 50[kHz], the first Duty Rate was made to increase gradually depending on the value of the detection were, 10[%] in the output voltage. As a result, the simulated Boost Power LED driver characteristics is in comparison with the design specifications, 5[%] or less as the error was approximated. So, when input 15[V] were offered, a stable output 24[V] were obtained, and Dimming Control through the adjustment of brightness and current consumption were obtained to possible result.