• Korean Journal of Plant Resources
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• v.11 no.1
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• pp.1-8
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• 1998

This study was conducted to establish mass propagation system from the axillary bud culture of chrysanthemum zawadskii H. which was used as material of medicinal plants. Shoot egeneration was better on MS medium with NAA and BA. The optimum concentraions of growth regulator for shoot regeneration differed depending on accessionsof C. Zawadskii. Shoot regeneration in Keungucheolcho was better on MS Medium with NAA 0.01mg/1 and BA 0.1mg/1 while Hyangrobonggucheocho was better with NAA 0.1mg/1and BA 0.3mg/1. Addition of NAA into medium was effective for induction of root from shoots regenerated. Shoot multiplcation was more effective when 10mg/1 spermine was added into medium than when other polyamines were treated ino medium . Randomly and specifically amplified polymorphic DAC banding patterns based on polymerase chain reaction (PCR) analysis were used to assess the genetic variation of plants regenerated from in vitro culture.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.453-455
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• 1993

In this research, the digital signal processing PC board which employs TI's TMS320C25 is implemented. The board can perform following functions. spectrum analysis of speech and repetitive signal, digital filters emulation by convolution, signal generation of sinusoidal wave, rectangular wave etc.. In this system, communications between PC and DSP board. program down-loading to DSP board and recording and graphic of acquired and processed data in DSP board are executed by PC. Parallel interface and buffer memory are used in communications. Data acquisition and operation are carried out in DSP board. Resultant data are transmitted to PC and output through DAC.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• Polymer(Korea)
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• v.36 no.4
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• pp.486-493
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• 2012

Photocurable sulfonated polyimide (SPI) polyelectrolyte containing chalcone group was prepared and fabricated on an alumina electrode pretreated with chalcone-containing silane-coupling agent. SPI films with bis(tetramethyl)ammonium 2,2'-benzidinedisulfonate ($Me_4N$-BDS)/4,4'-diaminochalcone (DAC)/pyromellitic dianhydride (PA)= 90/10/100 possessed very linear response(Y = -0.04528X+7.69446, $R^2=0.99675$) and showed resistance changing from 4.48 to $2.1k{\Omega}$ between 20 and 95 %RH. The response time for absorption and desorption measurements between 33 and 94 %RH% was about 79 s, which affirmed the high efficiency of crosslinked SPI film for rapid detection of humidity. A negative temperature coefficient showing $-0.49%RH/^{\circ}C$ was found and proper temperature compensation should be considered in future applications. Moreover, pretreatment of the substrates with chalcone-containing silane-coupling agent was performed to improve the water durability and the stability of the humidity sensors at a high humidity and a high temperature and long-term stability for 480 h. The crosslinked SPI films anchored to electrode substrate could be a promising material for the fabrication of efficient humidity sensors with superior characteristics compared to the commercially available sensors.

• Journal of Advanced Navigation Technology
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• v.12 no.2
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• pp.139-145
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• 2008

There has been lots of studies on communication systems using millimeter wave recently in many countries, specially in newly assigned 57GHz ~ 64GHz ISM band. Among those studies, IEEE 802.15.3c standard proposes OFDM (Orthogonal Frequency Division Multiplexing) systems for high data rate transmission support. But OFDM method has the PAPR (peak-to-Average Power Radio) problem The PAPR problem is to decline the performance of the transmission system due to signals distorted severely when passing through nonlinear components such as ADC/DAC and power amplifiers. In order to solve the problem of P APR, this paper suggests SSC (Sine Soft Clipping) and analyzes the PAPR, CCDF, PSD, BER by applying SAW(Surface Acoustic Wave) filter and power amplifiers to IEEE 802.15.3.c OFDM WPAN systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.129-132
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• 2003

In this paper, which sees the Strong-ARM SA1110 it used the main CPU and RTP in VoIP system. It will be able to apply the information communication field it embodied. It used the Tynux_box2 with the hardware side and it composed a VOIP system. And it used the RTP which is a real-time protocol in software control portion. The development environment of the paper that used the Target board and a Linux PC for connection used the RS-232C, USB connection, Ethernet LAN. The VoIP the environment for a communication used the wave file in the substitution which changes analog signal with the digital signal. And For the communication of the both sides it used the socket. This paper explained the fact that against a general technique from the operation of VoIP system. Using the Embedded linux development board which explained an operational process of the RTP protocol.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.713-718
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• 2016

Predicting precise specifications of differential mixed-signal circuits is a difficult problem, because analytically derived correlation between process variations and conventional specifications exhibits the limited prediction accuracy due to the phase unbalance, for most self-tests. This paper proposes an efficient prediction technique to provide accurate specifications of differential mixed-signal circuits in a system-on-chip (SoC) based on a nonlinear statistical nonlinear regression technique. A spectrally pure sinusoidal signal is applied to a differential DUT, and its output is fed into another differential DUT through a weighting circuitry in the loopback configuration. The weighting circuitry, which is employed from the previous work [3], efficiently produces different weights on the harmonics of the loopback responses, i.e., the signatures. The correlation models, which map the signatures to the conventional specifications, are built based on the statistical nonlinear regression technique, in order to predict accurate nonlinearities of individual DUTs. In production testing, once the efficient signatures are measured, and plugged into the obtained correlation models, the harmonic coefficients of DUTs are readily identified. This work provides a practical test solution to overcome the serious test issue of differential mixed-signal circuits; the low accuracy of analytically derived model is much lower by the errors from the unbalance. Hardware measurement results showed less than 1.0 dB of the prediction error, validating that this approach can be used as production test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.498-504
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• 2008

In this paper, an efficient hardware platform for the digital signal processing for OFDM Communication systems is presented. The hardware platform consists of a single FPGA, two DSPs with 8000 MIPS of maximum at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16 software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.