• Journal of the Korea Society for Simulation
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• v.8 no.4
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• pp.9-24
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• 1999

We describe a heterogeneous simulation framework, so called DEVS-HLA, in which conventional simulation models and the DEVS (Discrete Event System Specification) models are interoperable. DEVS-HLA conceptually consists of three layers: model layer, DEVS BUS layer, and HLA (High Level Architecture) layer. The model layer has a collection of heterogeneous simulation models, such as DEVS, CSIM, SLAM, and so on, to represent various aspects of a complex system. The DEVS BUS layer provides a virtual software bus, DEVS BUS, so that such simulation models can communicate with each other. Finally, the HLA layer is employed as a communication infrastructure, which supports several good features for distributed simulation. The DEVS BUS has been implemented on the HLA/RTI (Run-Time Infrastructure) and a simple example of a flexible manufacturing system has been developed to validate the DEVS-HLA.

• International Journal of Automotive Technology
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• v.6 no.4
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• pp.403-411
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• 2005

The bus is regarded as one of the most frequently used public transportation systems, the research and development on driving stability, safety, and convenience for drivers and passengers has tremendously increased in recent days. This paper investigated the design of the bus door mechanism composed of an actuator (or motor) and linkages. The bus door mechanism is divided into many types according to the coupling of the linkages and the driving system. The mathematical models of all types of door mechanism have been constructed for computer simulation. To design the bus door mechanism, we developed a simulation program, which automates the kinematic and dynamic analysis according to the input parameters of each linkage and the driving system. Using this program, we investigated the design parameters that affect the kinematic and dynamic characteristics of the bus door mechanism under various simulation conditions. In addition, simple examples are examined to validate the developed program.

• Journal of the Korea Society for Simulation
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• v.12 no.4
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• pp.95-102
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• 2003

Stream servers are for supplying multimedia stream data to users through the internet such as movies and music without discontinuation. A typical stream server is designed roughly by considering the characteristics of stream services and by employing processors, memory, PCI bus, Ethernet, TOE and disks. This study focuses on deciding the priority for using resources such as PCI bus, buffer memory and TOE buffer, which have limited capacities in a typical stream server. When the priorities for using limited resources are not given properly, the stream servers may not even function as originally designed. The simulation study shows that the top priority for using PCI bus for normal streaming services should be given to the operation that sends data from buffer memory to TOE buffer. Giving priority for using PCI bus to other operation such as sending data from disks to memory results in a deadlock phenomenon.

• Proceedings of the Korea Society for Simulation Conference
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• 2003.11a
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• pp.67-74
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• 2003

Stream servers are for supplying multimedia stream data to users through the internet such as movies and musics without discontinuation. A typical stream server is designed roughly by considering the characteristics of stream services and by employing processors, memory, PCI bus, Ethernet, TOE and disks. This study focuses on deciding the priority for using resources such as PCI bus, buffer memory and TOE buffer, which have limited capacities in a typical stream server. The simulation study shows that the top priority for using PCI bus for normal streaming services should be given to the operation that sends data from buffer memory to TOE buffer Giving priority for using PCI bus to other operation such as sending data from disks to memory results in deadlock Phenomenon.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.21 no.6
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• pp.70-86
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• 2022

An autonomous demand-responsive bus with mobility-on-demand service is an innovative transport compensating for the disadvantages of an autonomous bus and a demand-responsive bus with mobility-on-demand service. However, less attention has been paid to the quantitative impact assessment of the autonomous demand-responsive bus due to the technological complexity of the autonomous demand-responsive bus. This study simulates autonomous demand-responsive bus trips by reinforcement learning on a microscopic traffic simulation to quantify the impact of the autonomous demand-responsive bus. The Chungju campus of the Korea National University of Transportation is selected as a testbed. Simulation results show that the introduction of the autonomous demand-responsive bus can reduce the wait time of passengers, average control delay, and increase the traffic speed compared to the results with fixed route bus service. This study contributes to the quantitative evaluation of the autonomous demand-responsive bus.

• Journal of Korean Society of Transportation
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• v.5 no.2
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• pp.5-18
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• 1987

Buses arrive at a traffic intersection later than passenger cars by the amount of dwell time at previous bus stops. This late arrival of buses affects the total passenger delay at intersections especially in the street carrying large bus volume. The bus progression signal system in which the signal offset is given in favor of bus platoons was applied in the case area of Kangnam street in Seoul, and various effects were analyzed using the TRANSYT-7F simulation model. It was observed that the total passenger delay can be reduced significantly if the bus progression signal system is applied, and the most effective bus priority treatment is proved to be the bus progression signal system installed with exclusive bus lanes.

• Journal of the Korea Convergence Society
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• v.12 no.4
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• pp.217-228
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• 2021

After the integrated fare system has been applied, public transportation and transfer traffic increased. As a result, transfer passengers must be considered in the operation of the bus. Although previous studies have limitations due to utilizing deterministic mathematical models, which fails to reflect the stochastic movements of passengers and buses, in this study, a more realistic bus stop micro-simulation model is proposed. Based on the proposed simulation model, we represent the relationship between bus arrival interval and passenger wait time as a regression model and empirically show the differences between the cases with and without transfer passengers. Also, we propose a method converting passenger waiting time to cost and find optimal bus arrival interval based on the converted cost. It is expected the proposed method enables bottom-up decision making reflecting practical situation.

• Journal of the Korea Society for Simulation
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• v.2 no.1
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• pp.13-22
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• 1993

In a multiple-bus multiprocessor system in which processors and memory modulus are interconnected through system buses, time delay due to bus contention degrades system performance. In order to reduce such a problem , and optimal bus arbitration scheme and its hardware are neccessary. In this study, performaces of four arbitration schemes are analyzed and compared : fixed-priority, equal-priority, rotating-priority and round-robin priority schemes. For the study, the software simulator of a multiple-bus multiprocessor system is developed by using SLAM II. Simulation results show that, when memory sccesses are evenly distributed to all memory modulus, round-robin priority scheme provides the best performance. But when a hot spot exists, the use of the fixed priority scheme results in the shortest access time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1714-1719
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• 2003

Antilock Brake System (ABS) is indispensable safety equipment for vehicles today. In order to develop new ABS ECU suitable for pneumatic brake system of a bus, a Hardware In-the-Loop Simulation (HILS) System was developed. In this HILS, the pneumatic brake system of a bus and antilock brake component were used as hardware. For the computer simulation, the 14-Degree of Freedom (DOF) bus dynamic model was constructed using the Matlab/Simulink software package. This model was compiled and downloaded in the simulation board, where the Power PC processor was used for real-time simulation. Additional commercial package, the ControlDesk was used to monitor the dynamic simulation results and physical signal values. This paper will focus on the procedure and results of evaluating the ECU in the HILS simulation. Two representative cases, wet basalt road and $split-{\mu}$ road, were used to simulate real road conditions. At each simulated road, the vehicle was driven and stopped under the help of the developed ECU. In each simulation, the dynamical behavior of the vehicle was monitored. After enough tests in the laboratory using HILS, the parameter-tuned ECU was equipped in a real bus, which was driven and stopped in the real test field in Korea. And finally, the experiment results of ABS equipped vehicle's dynamic behavior both in HILS test and in test fields were compared.