• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.5
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• pp.921-928
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• 2011

This paper presents a new method of local voltage control to achieve coordinative control among UPFC(Unified Power Flow Controller) and conventional reactive compensation equipments, such as switched-shunt and ULTC(Under-Load Tap Changing) transformer. Reactive power control has various difficult aspects to control because of difficulty of system analysis. Recently, the progress of power electronics technologies has lead to commercial availability of several FACTS(Flexible AC Transmission System) devices. The UPFC(Unified Power Flow Controller) simultaneously allows the independent control of active and reactive power flows as well as control of the voltage profile. When conventional reactive power sources and UPFC are used to control system voltage, the UPFC reacts to the voltage deviation faster than the conventional reactive power sources. Keeping reactive power reserve in an UPFC during steady-state operation is always needed to provide reactive power requirements during emergencies. Therefore, coordination control among UPFC and conventional reactive power sources is needed. This paper describe the method to keep or control the voltage of power system of local area and to manege reactive power reserve using PSS/E with Python. The result of simulation shows that the proposed method can control the local bus voltage within the given voltage limit and manege reactive power reserve.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.10
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• pp.1699-1708
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• 2007

The optimal power flow(OPF) problem was introduced by Carpentier in 1962 as a network constrained economic dispatch problem. Since then, the OPF problem has been intensively studied and widely used in power system operation and planning. In these days, OPF is becoming more and more important in the deregulation environment of power pool and there is an urgent need of faster solution technique for on-line application. To solve OPF problem, many heuristic optimization methods have been developed, such as Genetic Algorithm(GA), Evolutionary Programming(EP), Evolution Strategies(ES), and Particle Swarm Optimization(PSO). Especially, PSO algorithm is a newly proposed population based heuristic optimization algorithm which was inspired by the social behaviors of animals. However, population based heuristic optimization methods require higher computing time to find optimal point. This shortcoming is overcome by a straightforward parallel processing of PSO algorithm. The developed parallel PSO algorithm is implemented on a PC cluster system with 6 Intel Pentium IV 2GHz processors. The proposed approach has been tested on the IEEE 30-bus system. The results showed that computing time of parallelized PSO algorithm can be reduced by parallel processing without losing the quality of solution.

• KIEE International Transactions on Power Engineering
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• v.5A no.4
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• pp.416-424
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• 2005

At present, the Korean electricity industry is undergoing restructuring and the Cost Based-generation Pool (CBP) market is being operated in preparation of a Two Way Bidding Pool (TWBP) market. In deregulated electricity industries, an integrated power market simulator is one of the tools that can be used by market participants and market operators analyzing market behaviors and studying market structures and market codes. In this regard, it is very important to develop an electricity market simulator that reflects market code providing a market operation mechanism. This paper presents the development of an integrated market simulator, called the Power Exchange Simulator (PEXSIM), which is designed to imitate the Korean electricity market considering the various features of the market operating mechanism such as uniform price and constrained on/off payment. The PEXSIM is developed in VB.NET and composed of five modules whose titles are M-SIM, P-SIM, O-SIM, T-SIM and G-SIM interfacing the Access database program. To verify the features and the performance of the PEXSIM, a small Two Way bidding market with a 12-bus system and a One Way bidding market for generator competition will be presented for the electricity market simulations using PEXSIM.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.240-241
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• 2006

Islanding operations of DG usually occur when power supply from the main utility is interrupted due to several reasons but the DG keeps supplying power into the distribution networks. These kinds of islanding conditions cause negative impacts on protection, operation, and management of distribution systems. Therefore, it is necessary to effectively detect the islanding conditions and swiftly disconnect DG from distribution network. This paper proposes the islanding detection algorithm for DG using the change of the voltage unbalance and the output power of DG. The proposed method effectively combines the conventional parameters for detecting the islanding conditions. The proposed methods were verified using the radial distribution network of IEEE 34 bus.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.371-373
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• 2005

An enhancement for a transmission and substation equipment in power system make the system impedance to be lower. In principle, if the system impedance become low, system stability will be better, but the fault current become very higher. It is a very big problem for CB operating. As a fact of CB operating performance, high amplitude of the fault current may cause CB operation failure because of exceeding standard value in TRV. So we simulated TRV by using the EMTP. Generally there are two types of TRV in actual power system. One is short line fault, the other is bus terminal fault. In this paper, we simulated the TRv at short line fault as installed current limit reactors to reduce fault current in 345kV ultra-high voltage system. Short line fault is caused from single line fault in transmission line.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.394-396
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• 2006

When developing a new GPS receiver module, the essential problems are evaluation of reliable algorithms, software debugging, and performance comparison between algorithms to find optimal solution. Most GPS receiver modules nowadays use a correlator to track signals from satellites and an MCU (Micro Controller Unit) to control operations of the entire module. The problem of software evaluation from MCU is very difficult, due to limitation of MCU resources and low ability of interfacing with user. Normally, user has to expense special tool kit for a limiting access to MCU but it is also hard to use. This article introduces an implementation of a GPS receiver test bed using correlator GP2021 interfacing with ISA (Industry Standard Architecture) PC bus. This way can give user complete control and visibility into the operation of the receiver, then user can easily debug program and test algorithms. For this article, the least square method is implemented to test the hardware and software performance.

• Journal of Power Electronics
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• v.18 no.2
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• pp.375-382
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• 2018

A novel active controlled primary current cutting-off zero-voltage and zero-current switching (ZVZCS) PWM three-level dc-dc converter (TLC) is proposed in this paper. The proposed converter has some attractive advantages. The OFF voltage on the primary switches is only Vin/2 due to the series connected structure. The leading-leg switches can obtain zero-voltage switching (ZVS), and the lagging-leg switches can achieve zero-current switching (ZCS) in a wide load range. Two MOSFETs, referred to as cutting-off MOSFETs, with an ultra-low on-state resistance are used as active controlled primary current cutting-off components, and the added conduction loss can be neglected. The added MOSFETs are switched ON and OFF with ZCS that is irrelevant to the load current. Thus, the auxiliary switching loss can be significantly minimized. In addition, these MOSFETs are not series connected in the circuit loop of the dc input bus bar and the primary switches, which results in a low parasitic inductance. The operation principle and some relevant analyses are provided, and a 6-kW laboratory prototype is built to verify the proposed converter.

• Journal of the Korea Safety Management & Science
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• v.17 no.1
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• pp.33-43
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• 2015

Modern systems development becomes more and more complicated due to the need on the ever-increasing capability of the systems. In addition to the complexity issue, safety concern is also increasing since the malfunctions of the systems under development may result in the accidents in both the test and evaluation phase and the operation phase. Light rail transit(LRT) with passenger capacity between bus and subway is driven by an unmanned control, so safety issues of LRT in emergency shall be considered more carefully than other rolling stock. Modern railway system is a complex system and many actions in emergency are required. In this view, interoperability approach is effective to identify the related elements in emergency. In this paper, we propose the method to generate the fire response scenario of unmann ed LRT based on the outputs of systems engineering architecture design methodology. The proposed method is could be contributed to establish more reliable and applicable fire response scenario.

• Journal of Korean Society of Transportation
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• v.18 no.3
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• pp.43-54
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• 2000

이 연구는 버스정보 시스템 설계에 필요한 운행시격 결정과 통행시간 예측을 위한 알고리즘 개발을 다룬다. 운행시격 결정 문제는 버스와 같은 대중교통 수단을 운영하는데 중요한 요소 중에 하나이다. 기존 연구는 버스 운행비용과 승객비용의 합을 최소로 하는 운행시 격을 찾는데 초점을 두고 이다. 이때 승객비용이란 승객 대기비용과 승객 교통비용의 합으로 이루어진다. 그런데 우리나라와 같이 버스회사 수입이 전액 운행수입에만 의존하는 경우엔 이러한 접근 방식이 타당하지 않다. 기존의 방식과 다르게 승객비용으로 승객 이탈비용을 사용하여 버스의 최적 운행시 격을 구하는 것이 이 연구의 목적이다. 먼저 정류장이 하나인 경우에 대해 해석적 방법으로 풀고, 정류장이 여러 개인 경우에 대해서는 시뮬레이션 기법을 적용한다. 또한 이 연구는 신뢰성이 높고 정확한 통행시간 예측정보를 산출하기 위해 2 단계 예측 기법과 전문가시스템을 이용하는 자료융합 알고리즘을 개발한다. 정확한 정보를 제공하려면 교통정보 수집원을 통해 얻는 자료가 정확해야 하고, 또한 교통상황 변화에 따라 실시간으로 통행시간을 예측하는 것이 필요하다. 이 연구는 AVL(Automatic Vehicle Location)시스템을 이용한 버스정보시스템에서 실시간 데이터와 과거 데이터를 융합하여 통행시간을 예측하는 알고리즘을 개발한다. AVL 데이터를 수집하는 과정에서는 경제성을 고려하여 데이터를 수집한다. 그리고, 버스의 운행관리와 정확한 도착예정시간을 예측하기 위해 AVL시스템을 통해 얻은 데이터의 패턴을 분석하고 유고상황을 감지한다.

• ETRI Journal
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• v.25 no.5
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.