• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 B
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• pp.800-803
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• 1996

This paper proposes the algorithm to solve emergency service restoration problems using efficient reconfiguration method in distribution system. In this algorithm, we try to avoid the blackout of important loads by considering service rank. It is possible to reconfigurate the system by using fuzzy inference results in which was reflected the expected distribution power, line capacity and service rank. A 27-bus, 32-branch model system is used to demonstrate the effectiveness of the proposed algorithm.

• 한국정보과학회논문지:소프트웨어및응용
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• 제35권2호
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• pp.91-104
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• 2008

서비스 지향 컴퓨팅(Service-Oriented Computing, SOC)은 배포된 서비스를 선택하고 조합하여 서비스 클라이언트가 원하는 기능을 제공하는 개발 방식이다. SOC는 향상된 비즈니스 기민성, 단축된 개발 시간과 같은 여러 장점을 제공한다. 이러한 장점을 극대화하기 위해서는 서비스의 선택과 조합이 동적으로 이루어져야 한다. 하지만 현재의 프로그래밍 언어, SOC 플랫폼, 비즈니스 프로세스 모델링 언어 (Business Process Modeling Language, BPML) 및 도구는 수동적 서비스 선택 또는 서비스의 정적 바인딩만을 지원하는 수준에 머물러 있다 각 클라이언트의 요구사항을 만족하는 서비스를 제공하기 위하여 해당 비즈니스 프로세스는 재구성 (reconfiguration)되고 재배포 (redeploy)되어야 하는 문제점이 있다. 따라서, 서비스 클라이언트의 다양한 요구에 맞게 서비스를 신속하고 유연하게 조합시키기 위하여 동적 선택기법이 필요하다. 본 논문에서는 엔터프라이즈 서비스 버스(Enterprise Service Bus, ESB) 기반의 동적 선택 핸들러 (Dynamic Selection Handler, DSH) 설계 기법을 제안한다. DSH의 네 가지 컴포넌트인 수행 리스너, 서비스 선택자, 서비스 바인더, 인터페이스 변환자에 대한 설계를 제시한다. DSH 설계 시에 적합한 디자인 패턴을 적용하여 컴포넌트의 재사용성이 높도록 설계한다. 마지막으로 제안한 DSH 설계의 실용성을 보이기 위해 ESB를 이용하여 DSH를 구현한다.

• Journal of Electrical Engineering and Technology
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• 제13권6호
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• pp.2145-2157
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• 2018

Congestion Management (CM) is an attractive research area in the electrical power transmission with the power compensation abilities. Reconfiguration and the Flexible Alternating Current Transmission Systems (FACTS) devices utilization relieve the congestion in transmission lines. The lack of optimal power (real and reactive) usage with the better transfer capability and minimum cost is still challenging issue in the CM. The prediction of suitable place for the energy resources to control the power flow is the major requirement for power handling scenario. This paper proposes the novel optimization principle to select the best location for the energy resources to achieve the real-reactive power compensation. The parameters estimation and the selection of values with the best fitness through the Symmetrical Distance Travelling Optimization (SDTO) algorithm establishes the proper controlling of optimal power flow in the transmission lines. The modified fitness function formulation based on the bus parameters, index estimation correspond to the optimal reactive power usage enhances the power transfer capability with the minimum cost. The comparative analysis between the proposed method with the existing power management techniques regarding the parameters of power loss, cost value, load power and energy loss confirms the effectiveness of proposed work in the distributed renewable energy systems.

• 대한원격탐사학회:학술대회논문집
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• 대한원격탐사학회 2006년도 Proceedings of ISRS 2006 PORSEC Volume I
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• pp.271-273
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• 2006

In this paper, we describe the MI2U ORB function which is a part of the flight software executed on SCU and controls MI2U/MI which is one of three payloads on COMS. The MI2U ORB function manages MI2U/MI redundancy and reconfiguration, monitors MI2U/MI equipment, performs FDIR, and provides the routing service of commands from Ground/IP (Interpreted Program) through the current used 1553 channel. The MI2U hardware achieves the interface between the SCU and the MI. The MI2U is connected to SCU through MIL-STD-1553B system bus. The MI2U has the internal redundancy but is used in cold redundancy. The MI2U ORB function considers that they are not expected to be simultaneously switched on. The connection combination between MI2U and MI is electrically cross-strapped. However the MI2U ORB function considers only two combinations (MI2U A + MI 1, MI2U B + MI 2). Other combinations can be manually achieved by ground in case of the emergency case.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.472-475
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• 2005

This paper present a robot controller developed for shipbuilding yard. Since shipbuilding process handles large work pieces and has dusty and noisy environment, the developed controller has separated architecture into main control part and servo control part. Main control part is located in control room while servo control part is located near robot with work pieces. Commutation between two parts is done through SynqNet and RS485. Air purging system is adapted to servo control part for better reliability. We aimed open architecture in both hardware and software architecture. For open hardware architecture, we employed Compact PCI (cPCI) because it is widely used bus system and very reliable. Since lots of commercial boards are available with cPCI interface, upgrade and reconfiguration is easy. For open software architecture, Windows XP�� Embedded is selected as operating system (OS), because it is very popular OS and most hardware vender supports device driver for the windows XP.

• 조명전기설비학회논문지
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• 제17권5호
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• pp.80-87
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• 2003

본 논문은 경험적인 탐색방법인 Reactive Tabu Search를 배전계통의 최적 재구성에 적용하였다. 일반적으로 Tabu search는 기울기가 감소하는 방향으로 탐색을 하기 때문에 적은 계산 시간으로 좋은 해를 얻을 수 있지만 초기의 계통 구성에 따라 수렴의 특성이 좌우되어 전역적인 최소해를 찾기가 어려운 단점이 있다 반면 RTS(Reactive Tabu search)는 reaction과 escape 메커니즘을 제공함으로써 파라미터 선정을 자동적으로 적응시키는 것이 가능하여 계통의 초기 구성에 관계 없이 전역적인 해를 적은 계산량으로도 찾을 수 있다. 렬 연구에서는 RTS의 reaction과 escape메커니즘 구현을 위하여 해싱 함수를 이용하였고 또한 제시된 방식을 32모선에 적용, 기존의 참고문헌과 비교함으로써 그 유용성을 입증하였다.

• 조명전기설비학회논문지
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• 제17권5호
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• pp.94-102
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• 2003

본 연구에서는 능동 데이터베이스를 이용하여 배전선로의 운전을 자동화하는 방안을 제시하였다. 기존의 선로운 전자동화 시스템에서는 수동형 데이터베이스를 사용으로 인위에 의한 실수로 광역정전 또는 과부하 구간의 파급등이 발생될 우려가 있었다. 그러나 제시된 능동 데이터베이스는 선로운전 자동화 시스템 데이터베이스의 상태를 항상 감시하고 스위치의 상태나 계통의 전류 또는 부하량이 변경되었을 경우 그에 상응하는 일련의 작업을 사용자의 개입없이 능동 규칙이용하여 데이터베이스 스스로 수행하도록 함으로써 인위에의한 실수를 최소화 할 수 있다. 제시된 방식을 실 계통인 서울의 K지점의 모의 배전계통에 적용하여 그 유용성을 입증하였다.

• 대한전기학회논문지:전력기술부문A
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• 제55권9호
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• pp.351-358
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• 2006

In this paper, DSPOCS(Digital Switchgear-Panel Operation and Control Solution) is designed, which is the intelligent inference based operation and control solution to obtain the safety and reliability of electric power supply in substation based on IED. DSPOCS is designed as a scheduled monitoring and control task and a real-time alarm inference task, and is interlinked with BRES(Bus Reconfiguration Expert System) in the required case. The intelligent alarm inference task consists of the alarm knowledge generation part and the real-time pattern matching part. The alarm knowledge generation part generates automatically alarm knowledge from DB saves it in alarm knowledge base. On the other hand, the pattern matching part inferences the real-time event by comparing the real-time event information furnished from IEDs of substation with the patterns of the saved alarm knowledge base.; Especially, alarm knowledge base includes the knowledge patterns related with fault alarm, the overload alarm and the diagnosis alarm. In order to design the database independently in substation structure, busbar is represented as a connectivity node which makes the more generalized graph theory possible. Finally, DSPOCS is implemented in MS Visual $C^{++}$, MFC, the effectiveness and accuracy of the design is verified by simulation study to the typical distribution substation.

• 한국정보과학회논문지:시스템및이론
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• 제27권3호
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• pp.277-286
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• 2000

스위치 형식의 네트워크이 많은 주목을 받고 있다. 그것은 높은 네트워크 성능을 요구하는 환경에 매우 적합하기 때문이다. 일반적인 공유매체 지역 네트워크는 만족할 만한 처리율과 지연시간을 제공하지 못한다. 특히 멀티미디어 어플리케이션이 증가하면서 통신 성능이 보다 중요시 되고 있다. 이러한 환경에서 스위치 형식의 네트워크는 우수한 성능을 보인다.스위치 형식의 네트워크는 높은 대역폭과 낮은 처리 시간을 얻을 수 있다. 따라서 스위치 형식의 지역네트워크를 구성할 때 고속(high-speed)의 스위치가 중요하다. 효율적인 스위치 디자인이 스위치 형식의 네트워크 성능을 향상시키는 중요한 요소인 것이다. 또한 멀티캐스트 메시지 처리의 중요성이 높아지면서, 효과적인 멀티캐스트를 지원하는 스위치의 설계가 필요하다. 기존의 컷-스루(cut-through) 스위칭 기술(switching technique)에서는 스위치 원소(switch element)의 구조를 변경시켜 데드락을 피하면서 멀티캐스팅이 가능하게 하였다. 그러나 처리율의 저하와 스위치 크기의 증가의 문제를 안고 있다. 따라서 하드웨어적으로 유니캐스트와 멀티캐스트를 분리함으로써 효율적인 멀티캐스팅을 가능하게 한다. 본 논문에서는 이러한 구조를 통해 멀티캐스팅에 있어서 성능 향상을 보이는 스위치 구조를 제안한다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}