• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.820-829
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• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.

• Journal of KIISE:Software and Applications
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• v.29 no.4
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• pp.211-224
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• 2002

As system become larger and more complex, it is important to correctly analyze and specify user's requirements. Use case modeling is widely used in Object-Oriented Analysis and Design(OOAD) and Component-Based Development(CBD). It is useful to mitigate the complexity of the requirements analysis. However, use cases are difficult to be structured, to explicitly represent non-functional requirements, and to analyze what is affected by changes of use cases. To alleviate these problems, we propose scenario-based goal-oriented approach for use case modeling. The approach is to apply goal-oriented analysis method to use case model. Since goal-oriented analysis method is not systematic and heuristics is considerably involved, we adopted scenarios as the basis for the goal extraction. The proposed method is applied to City Bus Information Subsystem(CBIS) in Intelligent Transport Systems(ITS) domain. The proposed approach helps software engineer to analyze what is affected by use case's changes and represent non-functional requirements.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.8 no.3
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• pp.52-63
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• 2009

Recently in Korea, in the case of metropolis, the urban signalized intersections are controlled by traffic information center or ITS center. Cheon-an City also established traffic information center through the 1st.-$\sim$3rd. ITS public construction and has managed this center that includes bus information service, traffic information collection and providing service, parking information service, and traffic responsive control system. In the Cheon-an metropolitan traffic signal operation, traffic signal controllers were grouped by the each main traffic flow axes and performed with coordinated signal timing for the signalized arterials, and also cycle and split changed by realtime traffic demands. Cheon-an urban traffic responsive control system was evaluated by intersection delay and speed, then it was verified that the delay decreased and vehicle speed improved. However, the rural signal control system to connect adjacency town was evaluated to have lower status than urban area due to the unimproved TOD (Time of day) plan. Therefore actuated signal control was examined for substitutive control system in isolated signal intersection. The aim of this article is to compare actuated signal control with TOD mode in the rural intersection of Cheon-an and to fine superiority of these two control mode, with evaluation of vehicle delay by using HCM(2000) method and by micro-simulation CORSlM. The result of field test show that actuated signal control gave better performance in delay comparison than the existing TOD signal control. And simulation outcome verified that non-optimized TOD has higher delay than optimized TOD mode, non-optimal actuated mode, and optimal actuated signal control mode. Particularly, these three modes delays had not different values according to the paired sample t-test. This is because small traffic demands were loaded in each links. This suggested actuated signal control is expected to be more effective than TOD mode in some rural isolated intersections which frequently need to survey for traffic volume.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.14-21
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• 2011

A 10b 500MS/s $0.13{\mu}m$ CMOS ADC is proposed for 4G wireless communication systems such as a LTE-Advanced and SDR The ADC employs a calibration-free single-channel folding architecture for low power consumption and high speed conversion rate. In order to overcome the disadvantage of high folding rate, at the fine 7b ADC, a cascaded folding-interpolating technique is proposed. Further, a folding amplifier with the folded cascode output stage is also discussed in the block of folding bus, to improve the bandwidth limitation and voltage gain by parasitic capacitances. The chip has been fabricated with $0.13{\mu}m$ 1P6M CMOS technology, the effective chip area is $1.5mm^2$. The measured results of INL and DNL are within 2.95LSB and l.24LSB at 10b resolution, respectively. The SNDR is 54.8dB and SFDR is 63.4dBc when the input frequency is 9.27MHz at sampling frequency of 500MHz. The ADC consumes 150mW($300{\mu}W/MS/s$) including peripheral circuits at 500MS/s and 1.2V(1.5V) power supply.

• Journal of Korean Society of Rural Planning
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• v.6 no.1 s.11
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• pp.19-28
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• 2000

Now in order to overcome the weakest points of the rural areas of the city of Kimje and, transform them into rural cultural villages which have local governing systems suitable to new localization age and activate this plan, we selected Daesan Village as a model village which had shown a lot of potentials in the basic research and studied it dividing it into the former part and the latter part. We studied Daesan village in the former part focusing on state analysis and basic ideas and in the latter part focusing on master plan and detail planning. We can summarize the conclusion like the followings. 1. Daesan Village located 8 kilometer away from the downtown Kimje and the city of Iksan respectably has comparatively good environment of good sunny place as an open field whose surrounding configuration of the ground consists of farming lands and low hills in front and rear. It has 38 farming households in all. 2. Human environment(인문환경); the village road whose width is about 4 meters is forming a flow system forking off into three. There is a route bus which operates three times a day even into the inside of the village. The main sources of revenue are vegetables in facilities, fruits and floriculture. Their average revenue is about 10.5 million won. 3. Here in DaeSan Village a legend dealing with Teasan literally meaning a big mountain consist of th village's tradition and you can see the tombs of a very faithful son and Anwi an army general in the age of the Japanese Invasion of Korea of 1592 to 1598 inside the village. 4. 85 out of the eitire population 141 whose age are over 20 showed very positive attitudes in a questionnaire about, making the village a cultural one and its development. 5. The basic of planned ideas is to increase the revenue of the farming household by making the village a professional farming one which has a state-of the-art production facility and agricultural technique. It is to make the village the one where people can enjoy the sense of the rural life and the farmer can enjoy their lives through consumptive and consistant leisure and resting activities. 6. We are planning to make entrance space, life space, rest and sport space, and cultural space considering the characteristics of the village and the demand of the resident. We are also planning to make tile entire city of Kimje an information transmitting base in short and long term perspectives. 7. DaeSan Village was planned as a place where tradition and the future exist together. On the basis of this concept we planned future programs for Daesan Village and in the latter part of the study master plans and detail plans will be continued.the regional agricultural condition. The development permissions were only during the period of restricted to use ($1979.12{\sim}1993.11$). We propose that the authority of development permission should be given to the local autonomy government, because the local government has the knowledge of its individual agricultural conditions.