• Journal of Korean Society of Transportation
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• v.17 no.2
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• pp.137-147
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• 1999

This paper studies on the optimal bus network design in the framework of the set covering theory. The theory enables to cover passenger's loading and alighting areas as the set, and maximize the covering set as much as possible. In other words, it calculates the minimal set of the bus routes for covering whole bus passengers demand. After the optimal set of the bus routes is generated by the set covering theory, multimodal traffic equilibrium assignment is used for evaluating the generated set in terms of passenger's mode and route choice behavior. Whilst most previous works on it have been based on analyzing a specific route in a limited area, this study seeks to optimize the whole bus network.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.17 no.2
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• pp.87-97
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• 2018

Bus, a major transportation mode, doesn't have a systematical evaluation system for dangerous driving behavior yet. This paper analyzes the characteristics and pattern of bus driving behavior using Digital Tacho Graph(DTG) data on express bus. 8 types of dangerous driving behavior were considered according to timeslot, the day of week and weather condition. As results, rapid acceleration, rapid left right turn and rapid deceleratio accounted for more than 97% and relatively high percentages were shown in dawn, on Friday and on the clear day, respectively. From the statistical analysis, correlation between the dangerous driving types and difference according the timeslot were found, and 3 groups considering the level of the dangerous driving were suggested. This study contributes to setting an efficient and reliable eduction system for using driving simulators.

• Journal of IKEEE
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• v.28 no.1
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• pp.116-122
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• 2024

AMBA AHB-Lite bus is widely used in on-chip bus protocol for low-power and cost-effective SoC. However, it lacks built-in error detection and correction for end-to-end data integrity. This can lead to data corruption and system instability, particularly in harsh environments like automotive applications. To mitigate this problem, this paper proposes the application of SEC-DED (Single Error Correction-Double Error Detection) to AMBA AHB-Lite bus. It aims not only to detect errors in real-time but also to correct them, thereby enhancing end-to-end data integrity. Simulation results demonstrate real-time error detection and correction when errors occur, which bolsters end-to-end data integrity of automotive on-chip bus.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.33-43
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• 1993

Lock mechanism is essential for synchronization on the multiprocessor systems. Lock mechanism needs to reduce the time for lock operation in low lock contention. Lock mechanism must consider the case of the high lock contention. The conventional lock control scheme in memory results in the increase of bus traffic and memory utilization in lock operation. This paper suggests a lock scheme which stores the lock data in cache and manages it efficiently to reduce the time spent in lock operation when the lock contention is low on a multiprocessor system built on HiPi-bus(Highly Pipelined bus). This paper also presents the design of the HIPi-CLOCK (Highly Pipelined bus Cache LOCK mechanism) which transfere the data from on cache to another when the lock contention is high. The designed simulator compares the conventional lock scheme which controls the lock in memory with the suggested HiPi-CLOCK scheme in terms of the RMW(Read-Modify-Write) operation time using simulated trace. It is shown that the suggested lock control scheme performance is over twice than that of the conventional method in low lock contention. When the lock contention is high, the performance of the suggested scheme increases as the number of the shared lock data increases.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.53-54
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• 2015

기존의 IEC 61850 표준 적용 국내 디지털변전소는 Station 레벨에 한정되어 구축되어 왔다. 향후 구축될 Process 레벨을 포함한 풀(Full) 디지털 변전소 디지털화는 디지털변전소 운전에 있어 중요하고 긴급한 신호인 Process bus를 통한 SV와 GOOSE신호의 전송으로 이루어지고 있다. Process bus를 활용한 배전선로 보호용 통합 IED는 GIS 등 변전소 전력설비로부터 전압과 전류 값을 MU(Merging Unit)를 통해 공급받아 각 구간의 Bay 혹은 Bank단위로 통합적인 보호 기능을 수행하고, 주 IED와 예비 IED가 서로의 상태를 상호 감시하여 보호기능의 이중화를 이루어야 하고, Sampled Value를 처리하기 위한 정밀한 시각동기화 기능을 갖추어야 한다. 만약, Process bus 시스템의 문제로 인해, 지연과 손실이 발생한다면 변전소 보호 제어에 영향을 줄 수 있으므로 Process bus를 디지털변전소에 적용하기 위해서는 Process bus 기반의 네트워크시스템에 연결된 MU와 IED가 송수신하는 SV와 GOOSE를 손실과 지연없이 전송할 수 있는지를 분석해야 한다. 본 연구에서는 디지털변전소 네트워크 시뮬레이션 시험을 통해, 배전선로용 통합 IED의 성능검증을 위해 Process bus 네트워크 시스템을 설계하고 시뮬레이션 시험을 수행하여 이를 통해 향후 국내의 Process bus 디지털변전시스템 구축을 위한 효과적인 네트워크 시스템 설계방법을 제시하고자 한다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.10
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• pp.509-516
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• 2001

Isolated phase bus(IPS) has a special structure for carrying large current generated by a generator to a main transformer. In the analysis of IPB, the understanding of the magnetic field distribution generated by large current is important. Especially, while the bus conductor current is flowing, almost same amount of current as bus conductor current is induced in the enclosures under the influence of time varying magnetic field, and therefore the large electric loss and the deterioration of insulating capability might occur due to Joule heating effect. Hence for the optimal design of IPB satisfying the condition to minimize the loss, the accurate analysis of magnetic field distribution and the eddy current characteristics of three phase isolated phase bus have been investigated. In the analysis of time varying magnetic field, instead of finite difference method(FDM) which is generally used, finite element method with phasor concept is investigated under the assumption that the bus current is purely sinusoidal. The characteristics is studied along the phase angle by comparing the effect of eddy current on the magnetic field distribution with the case that eddy current is not considered, and also the effect of material, thickness and radius of enclosure on the eddy current distribution is discussed.

• Proceedings of the KIEE Conference
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• 2008.04a
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• pp.193-194
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• 2008

This paper defines the electrical interfaces and limited items to integrate Ka-band communication payload on the satellite system, which includes the detailed interfaces such as bus voltage and data bus according to the related COMS requirements. And the BUS Electrical Interface Simulator introduces to use during the course of validating and accepting between the KA-Band payload and their EGSE. These interface design results are fully validated through the testing with the BEIS and is compliant with the satellite interface control interface requirements.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.7
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• pp.254-260
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• 1983

In this paper a basic design procedure for programmable instruments of IEEE-488 BUS system has been discussed by designing a specific programmable frequency counter with its hardware and software. The designed programmable frequency counter has a programmable range switch and a function of the programable number of measurements. It contains five basic functions(Talker. Listener, Source handshake, Accepter handshake and Controller) of a IEEE-488 BUS and the Device-Trigger as a supplimentary function. The hardware has been built along with 6800 MPU and 68488 GPIA, and its software has included initialization, interrupt handler, BI.GET,BO and controller routines, The designed system given in this paper has been successfuly tested via some experiments.

• Transactions of the Korean Society of Automotive Engineers
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• v.7 no.6
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• pp.156-164
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• 1999

The body structure of a bus is generally assembled by using various spot welded box sectional members. The shape of window pillar joint is ordinarily built up by T-type member. It has been shown that T-type member has problems like high stress concentrations, low fatigue strength and low structural rigidity. In this study, to solve these problems a new approach to optimize the design of the bus window pillar joint was tried by FEM analysis and experiments. To describe the shape of the gusset connecting the vertical and horizontal members of the T-type window pillar joint B-spline curve was adopted and this curve was optimized . It was found that the new model developed could effectively improve fatigue durability an structural rigidity.

• Transactions of the Korean Society of Automotive Engineers
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• v.7 no.7
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• pp.195-201
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• 1999

In Rollover crashes, the development of bus structure to ensure the maintenance of survival space for passengers is very important . So, this paper focuses on understanding the possibility of efficient structural development considering rollover strength through computer simulation using the commercial code, LS-DYNA3D at the initial stage of vehicle development structural members, and impact boundary conditions required by ADR59(Australian Design Rule 59)were applied. In order to confirm the validity of the computational results, the test results. After the usefulness of this method of analysis was confirmed , we have proposed the effective modificationfor rollover strength.