• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.59 no.12
• /
• pp.2195-2201
• /
• 2010

The VBC(Voltage Bus Conditioner) is a bidirectional DC-DC converter with the energy storage for damping the instability and any transients of bus voltage in the DC DPS(Distributed Power System). This paper presents the PI(Proportional Integration) controller for the VBC. The PI controller is not only damping the bus transient, but also keeping the storage voltage level. Matlab Simulink simulation and experimental results are presented by validity of the proposed control technique.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.499-502
• /
• 1999

This paper presents a PCI (Peripheral Component Interconnect) controller embedded in a multimedia processor, called FLOVA (FLOating point VLIW Architecture), targeting for 3D graphics applications. Fast I/O interfaces are essential for multimedia processors which usually handle large amount of multimedia data. Therefore, in FLOVA, PCI bus is adopted for I/O interface due to fast burst transaction. However, there are several problems in implementation and verification to use burst transaction of PCI. It is difficult to handle data transaction between two units which have two different operating frequency. FLOVA has more higher operating frequency about 100MHz than that of PCI local bus and it makes lower utilization of FLOVA bus. Also, traditional simulation is not sufficient for verification of PCI functionality. In this paper, we propose buffering schemes to implement the PCI controller with wide bandwidth and high bus utilization. Also, this paper shows how to verify the PCI controller using real PCI bus environments before its fabrication.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.2
• /
• pp.75-79
• /
• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• Proceedings of the KIEE Conference
• /
• 2000.07c
• /
• pp.1990-1992
• /
• 2000

Isolated phase bus is, as a special bus which allows large current from a generator to main transformer, composed of main conductor, enclosure and auxiliary equipments such as insulating bellows, bus elbows, support insulator, etc. To develop this kind of high power devices, it is required to secure the technique of selection of conducting and insulating materials, basic arrangement skills, and analysis on eddy current which causes temperature increase in enclosures. By the way, these techniques are based on the analysis of electromagnetic phenomena for high voltage and large current. In this study, an electromagnetic field analysis program is developed and applied to the isolated phase bus. which could be the basic numerical method for the analysis design and modifying isolated phase bus.

• ETRI Journal
• /
• v.32 no.4
• /
• pp.540-547
• /
• 2010

One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.15 no.2
• /
• pp.88-97
• /
• 1990

In this paper, DPA bus is proposed for implementation of MC 68000 based tightly-coupled multiprocessor system. The DPMC and arbiter are designed that the local memory of each PE can accept memory request both from a local processor and from the system bus. The performance of the proposed system bus is evaluated by Stochastic Petri Net(SPN) system modeling. The processing power, the efficiency, and the utilization of system bus are simulated for various load factors.

• Journal of Internet Computing and Services
• /
• v.10 no.2
• /
• pp.125-132
• /
• 2009

The goal of our research is to develop a smart context-aware guide system that provides a smart and personalized guide services based on implicit awareness of context. As a context-aware guide application, we have developed a location-aware smart bus guide system for Seoul based on PDA and GPS. It guides users to the nearby bus stops and provides users with information about the bus lines at the bus stops.

• Transactions of the Korean Society of Automotive Engineers
• /
• v.15 no.1
• /
• pp.56-63
• /
• 2007

In case of bus rollover, the body structure of the bus should be designed to ensure the survival space for passengers. So, this study focuses on evaluating rollover strength through a computer simulation using the commercial code, LS-DYNA3D at the initial stage of vehicle development. For this study, section structure was modeled using a simple beam element, and impact boundary conditions required by ECE(Economic Commission for Europe) regulation No.66 were applied. In order to confirm the validity of the beam element bus model, the results compared with the test results and shell element bus model. The analysis errors from beam element bus model are due to the difference in strain energy of joint area between beam and shell model. In this study, a method for the joint modeling was suggested by using nonlinear springs to which the collapse mechanisms were applied.

• Journal of Korea Society of Industrial Information Systems
• /
• v.24 no.4
• /
• pp.21-28
• /
• 2019

As ICT technology develops, researches on the construction of communication system for the rapid processing using ICT technology in case of traffic accidents are actively under way. e-Call (Emergency call) is a vehicle ICT-based emergency rescue system that recognizes and reports traffic accidents. On the other hand, the existing bus information system collects the positioning data through the position tracking system mounted on the bus and transmits it to the center, and then provides various services based on the bus information of the collected buses. In this paper, we designed and implemented an emergency rescue system that using the existing bus information system in order to deal with accidents, failures, and emergency situations on public buses quickly.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.8
• /
• pp.33-44
• /
• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.