• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10A
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• pp.996-1002
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• 2006

USB(Universal Serial Bus) is one of the most popular communication interfaces. When USB is used in an extended range, especially configurating In-home network by connecting multiple digital devices each other, USB interface uses the bandwidth in the way of TDM (Time Division Multiplexing) so that the bottleneck of bus bandwidth can be brought. In this paper, the more effective usage of bus bandwidth to overcome this situation is introduced.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2499-2502
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• 2005

Universal Serial Bus (USB) is one of the most popular communication interfaces. When USB is used in more extended range, especially configuring home network by connecting multiple digital devices each other, USB interface uses the bandwidth in the way of Time Division Multiplexing (TDM) so that the bottleneck of bus bandwidth can be brought under the heavy traffic. In this paper, the more effective usage of bus bandwidth to overcome this situation is introduced. Basically, in order to realize the system for transferring real-time moving picture data among digital information devices, we analyze USB transfer types and descriptors and introduce the method to enhance the detailed performance of isochronous transfer that is one of USB transfer types.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.80-86
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• 2010

The conventional bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in arbitrating the bus. The efficiency of bus usage can be determined by the selection of arbitration method. Fixed Priority, Round-Robin, TDMA and Lottery arbitration policies are studied in the conventional arbitration method where the bus priority is primarily considered. In this paper, we propose the arbitration method that calculates the bus utilization of each master. Furthermore, we verify the performance compared with the other arbitration methods through TLM(Transaction Level Model). From the results of performance verification, the arbitration methods of Fixed Priority and Round-Robin can not set the bus utilization and those of TDMA and Lottery happen the error of 50% and 70% respectively compared with bus utilization set by user in more than 100,000 cycles. On the other hand, the bandwidth-award bus arbitration method remains the error of less than 1% since approximately 1000 cycles, compared with bus utilization set by user.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.33-39
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• 2011

H.264 decoders usually have pipeline architecture by a macroblock or a 4 ${\times}$ 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. Adaptive pipeline architecture for H.264 decoders has been proposed for efficient decoding and lower the requirement of the bandwidth for the memory bus. However, it requires a controller for the adaptive priority control to utilize the advantage. We propose a smart bus arbiter that replaces the controller. It is introduced to adjust the priority adaptively the QoS (Quality of Service) control of the decoding process. The smart arbiter can be integrated the arbiter of bus systems and it works when certain conditions are met so that it does not affect the original functions of the arbiter. An H.264 decoder using the proposed architecture is designed and implemented to verify the operation using an FPGA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.9-18
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• 2005

This paper proposes the novel synchronous segmented bus architecture that has the pipeline bus architecture based on OCP(open core protocol) and the memory-oriented bus for MPEG system. The proposed architecture has bus architectures that support the memory interface for image data processing of MPEG system. Also it has the segmented hi-directional multiple bus architecture for multitasking processing by using multi -masters/multi - slave. In the scheme address of masters and slaves are fixed so that they are arranged for the location of IP cores according to operational characteristics of the system for efficient data processing. Also the bus architecture adopts synchronous segmented bus architecture for reuse of IP's and architecture or developed chips. This feature is suitable to the high performance and low power multimedia SoC systum by inherent characteristics of multitasking operation and segmented bus. Proposed bus architecture can have up to 3.7 times improvement in the effective bandwidth md up to 4 times reduction in the communication latency.

• Proceedings of the Korea Contents Association Conference
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• 2004.11a
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• pp.327-332
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• 2004

USB(Universal Serial Bus) is one of the most popular communication interfaces. When USB is used in an extended range, especially configurating In-home network by connecting multiple digital devices each other, USB interface uses the bandwidth in the way of TDM(Time Division Multiplexing) so that the bottleneck of bus bandwidth can be brought. In this paper, the more effective usage of bus bandwidth to overcome this situation is introduced. Basically, in order to realize the system for transferring realtime moving picture data among digital information devices, we analyze USB transfer types and Descriptors and introduce the method to upgrade detailed performance of Isochronous transfer that is one of USB transfer types. In the case that Configuration descriptor of a device has Interface descriptor that has two AlternateSetting, if Isochronous transfers are not processed smoothly due to excessive bus traffic, the application of the device changes AlternateSetting of the Interface descriptor and requires a new configuration by SetInterface() request. As a result of this adaptive configuration, the least data frame rate is guaranteed to a device that the sufficient bandwidth is not alloted. And if the bus traffic is normal, the algorithm to return to the original AlteranteSetting is introduced. this introduced method resolve the bottleneck of moving picture transfer that can occur in home network connected by multiple digital devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.35-44
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• 2005

SoC(systnn-on-a-chip) requires high bandwidth system bus for performing multiple functions. Performance of the system is affected by bandwidth of the system bus. In this paper, for efficient management of the bus resource on a SoC platform, we present a latency model of the shared bus organized by multiple layers. Using the latency model, we can analyze latencies of the shared bus on a SoC. Moreover we evaluate a throughput of the bus and compare with needed throughput of the SoC platform including IPs such as MPEG or USB 2.0. And we can use the results as a criteria to find out an optimal bus architecture for the specific SoC design. For verifying accuracy of the proposed model, we compared the latencies with the simulation result from MaxSim tools. As the result of simulation, the accuracy of the IS model for a single layer and multiple layer are over $96\%\;and\;85\%$ respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.618-636
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• 1997

DQDB(Distributed Queue Dual Bus) protocol, the IEEE 802.6 standard protocol for metropolitan area networks, does not fully take advantage of the capabilities of dual bus architecture. Although fairness in bandwidth distribution among nodes is improved when using so called the bandwidth balancing mechanism, the protocol requires a considerable amount of time to adjust to changes in the network load. Additionally, the bandwidth balancing mechanism leaves a portion of the available bandwidth unused. In a high-speed backbone network, each node may act as a bridge/ router which connects several LANs as well as hosts. However, Because the existence of high speed LANs becomes commonplace, the congestionmay occur on a node because of the limitation on access rate to the backbone network and on available buffer spaces. to release the congestion, it is desirable to install some congestion control algorithm in the node. In this paper, we propose an efficient congestion control mechanism and fair and waster-free MAC protocol for dual bus network. In this protocol, all the buffers in the network can be shared in such a way that the transmission rate of each node can be set proportional to its load. In other words, a heavily loaded node obtains a larger bandwidth to send the sements so tht the congestion can be avoided while the uncongested nodes slow down their transmission rate and store the incoming segments into thier buffers. this implies that the buffers on the network can be shared dynamically. Simulation results show that the proposed probotol significantly reduces the segment queueing delay of a heavily loaded node and segment loss rate when compared with original DQDB. And it enables an attractive high throughput in the backbone network. Because in the proposed protocol, each node does not send a requet by the segment but send a request one time in the meaning of having segments, the frequency of sending requests is very low in the proposed protocol. so the proposed protocol signigificantly reduces the segment queuing dely. and In the proposed protocol, each node uses bandwidth in proportion to its load. so In case of limitation of available buffer spaces, the proposed protocol reduces segment loss rate of a heavily loaded node. Bandwidth balancing DQDB requires the wastage of bandwidth to be fair bandwidth allocation. But the proposed DQDB MAC protocol enables fair bandwidth without wasting bandwidth by using bandwidth one after another among active nodes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.117-126
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• 2012

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively