• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.896-904
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• 1987

In this paper, a design method for sequential circuit which is easy to have Built-in Self Test is kproposed using the functional advantages of multifunctional BILBO and LSSD. To achieve the hardware reduction, it is designed that a multifunctional BILBO has double operational functions of NLFSR and LFSR, when neccessary, and that test signal could be used as an input-output signal in the same line. By applying the proposed multifunctional BILBO to the sequential PLA, the test patterns and the additional circuit could be reduced in test operation and the propagation delay is vanished in normal operation, as we expected. Above them, the partitioned method for large scale sequential circuit is also suggested and it is observed that test patterns and additional circuit in them reduced by this method.

• Journal of KIISE:Software and Applications
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• v.29 no.1_2
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• pp.65-79
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• 2002

Object-oriented frameworks need to be systematically tested because they are reused in developing many applications software. They also need additional testing whenever they are extended for reuse. Frameworks, however, have properties that make it difficult to control and observe the testing of the parts that were modified and extended. In this paper, we describe the method of embedding test components as BIT(Built-In Test) into the framework's hot spots in order to efficiently detect the faults through testing that occurred while implementing application programs by modifying and extending the framework. The test components embedded into a framework make it easy to control and observe testing the framework, and thereby improve the testability of frameworks. Test components designed by the method proposed in this paper can be dynamically attached and detached to/from hot spots of a framework without changes or intervention to the framework code.

• Journal of the Korea Institute of Military Science and Technology
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• v.15 no.2
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• pp.111-120
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• 2012

Built-In-Test is a design feature in more and more advanced weapon system. During development test and evaluation(DT&E) it is critical that the BIT system be evaluated. The BIT system is an integral part of the weapon system and subsystem. Built-In-Test assists in conducting on system and subsystem failure detection and isolation to the Line Replaceable Unit(LRU). This capability reduces the need for highly skilled personnel and special test equipment at organizational level, and reduces maintenance down-time of system by shortening Total Corrective Maintenance Time. During DT&E of weapon system the objective of BIT system evaluation is to determine BIT capabilities achieved and to identify deficiencies in the BIT system. As a result corrective actions are implemented while the system is still in development. Through the use of the reiterative BIT evaluation the BIT system design was corrected, improved, or updated, as the BIT system matured.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1038-1045
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• 1994

In this paper, algorithm and built-in test circuit for testing all PSF(Pattern Sensitive Fault) occuring in CAM(Content Addressable Memory) are proposed. That is, built-in test circuit that uses minimum additional circuit without external equipment is designed. Additional circuit consist`s of parallel comparator, error detector, and modified decoder for parallel testing. Besides, the study on eulerian path for effectiv test pattern is carried out simultaneously. Consequently, using proposed algorithm, we can test all contents of CAM with 325+2b(b:number of bits) operations regardless of number of words. The area occupied by test circuit is about 7.5% of total circuit area.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1004-1007
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• 2005

This paper presents a programmable RF BIST (Built-in Self-Test) circuit for low noise amplifiers. We have developed a new on-chip RF BIST circuit that measures RF parameters of low noise amplifier (LNA) using only DC measurements. The BIST circuit contains test amplifier with programmable capacitor banks and RF peak detectors. The test circuit utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the mathematical equations. Our on-chip BIST can be self programmed for 1.8GHz, 2.4GHz and 5.25GHz LNA for GSM, Bluetooth and IEEE802.11g standards.

• Journal of the Korean Society of Clothing and Textiles
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• v.29 no.6
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• pp.837-846
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• 2005

The purpose of this study is to suggest a standard of guidance for testing the performance and safety of motorcycle jacket with built-in airbag. The method of testing were as follows: The effects of the motorcycle jacket with built-in airbag are experimentaly investigated according to neck injury of FMVSS 208. The experiment consists of the crash simulation test by shield and the impact test. The head and neck injuries are evaluated based on industrial standards. Also, the displacements of the head and neck and chest are observed by film analysis. Using the results of the crash simulation test, neck injury$(N_ij)$ is discussed and the peak chest deflection of the results of the impact test, chest injury is pursued. Neck injury$(N_ij)$ of the result of the crash test show that the chance of a serious wound is $18\%$ if rider wear the R&D motorcycle jacket with built-in airbag(Type A). Chest injury is expected by peak chest deflection of the result of the impact test. The result of the peak chest deflection show that the reduction effect in chest injury of Type A motorcycle jacket is $10.3\%$.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.914-917
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• 2008

A quad-functional built-in test circuit has been developed for DRAM-frame-memory embedded SOG-LCDs. The quad function consists of memory test, display test, serial transfer test, and parallel transfer test which is the normal operation mode for our SOG-LCD. Results of memory and display tests are shown.

• Journal of KIISE:Software and Applications
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• v.32 no.8
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• pp.704-716
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• 2005

Assembling new software systems from Prepared components is an attractive alternative to traditional software development method to reduce development cost and schedule dramatically. However, if separately developed components are tested, integrated and verified with unreasonable effort and high cost, it would not be an effective way to software development. Components are not distributed in the shape of white-box source code so that should be hard to validate and test in new application environment. For solving this problem, built-in tester components are suggested to check the contract-compliance of their server components. If components have various and complex function, built-in tester should be heavy and unflexible to test in composition of components. This paper suggests enhancing automated wrapper technique which substitutes with built-in tester components and shows the usability of the wrapper by design and implementation. Component testing in this way reduces the cost and effort associated with preparation of component testing and makes the various test experiments in components assembly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.85-97
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• 2002

STUMPS has been widely used for built-in self-test of scan design with multiple scan chains. In the STUMPS architecture, there is very high correlation between the bit sequences in the adjacent scan chains. This correlation causes circuits lower the fault coverage. In order to solve this problem, an extra combinational circuit block(phase shifter) is placed between the LFSR and the inputs of STUMPS architecture despite the hardware overhead increase. This paper introduces an efficient test pattern generation technique and built-in self-test architecture for sequential circuits with multiple scan chains. The proposed test pattern generator is not used the input of LFSR and phase shifter, hence hardware overhead can be reduced and sufficiently high fault coverage is obtained. Only several XOR gates in each scan chain are required to modify the circuit for the scan BIST, so that the design is very simple.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.1-9
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• 1998

A new parallel test algorithm and a built-in self test (BIST) architecture are developed to test various types of functional faults efficiently in content addressable memories (CAMs). In test mode, the read oepratin is replaced by one parallel content addressable search operation and the writing operating is performed parallely with small peripheral circuit modificatins. The results whow that an efficient and practical testing with very low complexity and area overhead can be achieved.