• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.7
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• pp.994-1002
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• 2013

This study suggests a generalized availability and safety evaluation model to evaluate the influences to the system's fault tolerant capabilities depending on automatic fault detection function such as the automatic periodic testings. The conventional evaluation model of automatic fault detection function deals only with the self diagnostics, and supposes that the fault detection coverage of self diagnostics is always constant. But all of the fault detection methods could be degraded. For example, the periodic surveillance test has the potential human errors or test equipment errors, the self diagnostics has the potential degradation of built-in logics, and the automatic periodic testing has the potential degradation of automatic test facilities. The suggested evaluation models have incorporated the loss or erroneous behaviors of the automatic fault detection methods. The availability and the safety of each module of the safety grade platform have been evaluated as they were applied the automatic periodic test methodology and the fault tolerant evaluation models. The availability and safety of the safety grade platform were improved when applied the automatic periodic testing. Especially the fault tolerant capability of the processor module with a weak self-diagnostics and the process parameter input modules were dramatically improved compared to the conventional cases. In addition, as a result of the safety evaluation of the digital reactor protection system, the system safety of the digital parts was improved about 4 times compared to the conventional cases.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5B
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• pp.685-691
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• 2001

본 논문은 4단계 파이프 라인과 VLIW (Very Long Instruction Word) 구조를 갖는 FLOVA라는 DSP 프로세서의 테스트용이 설계 기법을 다룬다. Full-scan design, BIST(Built-In-Self-Test), IEEE 1149.1의 기법들이 플립플롭과 floaing point unit, 내장된 메모리, I/O cell 등에 각각 적용되었다. 이러한 기법들은 테스트 용이도의 관점에서 FLOVA의 구조에 적절하게 적용되었다. 본 논문에서는 이와 같이 FLOVA에 적용된 테스트 용이 설계의 특징들을 중심으로 상세하게 기술한다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.6
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• pp.403-408
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• 2005

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random This paper proposes and presents a new efficient network architecture for Reflective Memory System (RMS). A time to copy shared-data among nodes effects critically on the entire performance of the RMS. In this paper, the recent researches about the RMS are investigated and compared. The device named Topology Conversion Switch(TCS) is introduced to realize the proposed network architecture. One of the RMS based industrial control networks, Ethernet based Real-time Control Network (ERCnet), is adopted to evaluate the performance of the proposed network architecture for RMS.

• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.67-71
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• 1999

In this paper, we design circuits embedded in memory chip which perform memory testing algorithms using BIST scheme to reduce testing time and cost for testing. In order to implement circuits for MSCAN, Marching and checkerboard test algorithms, which have widely used in memory testing, we survey structure of the BIST circuits and describe each block of BIST circuits by using VHDL. Thereafter, We verify behavior of each VHDL coding block and extract BIST circuits for target testing algorithms by CAD tool for simulation and synthesis. Extracted circuits have very low area overhead.

• Restorative Dentistry and Endodontics
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• v.29 no.3
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• pp.273-280
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• 2004

The purpose of this study was to evaluate the etching effects and bond strength of total etching and self-etching adhesive system on unground enamel using scanning electron microscopy and microtensile bond strength test. The buccal coronal unground enamel from human extracted molars were prepared using low-speed diamond saw. Scotchbond Multi-Purpose (group SM). Clearfil SE Bond (group SE), or Adper Prompt L-Pop (group LP) were applied to the prepared teeth. and the blocks of resin composite (Filtek Z250) were built up incrementally. Resin tag formation was evaluated by scanning electron microscopy. after removal of enamel surface by acid dissolution and dehydration. For microtensile bond strength test. resin-bonded teeth were sectioned to give a bonded surface area of $1\textrm{mm}^2$. Microtensile bond strength test was perfomed. The results of this study were as follows. 1. A definite etching pattern was observed in Scotchbond Multi-Purpose group. 2. Self-etching groups were characterized as shallow and irregular etching patterns. 3. The results (mean) of microtensile bond strength were SM: 26.55 MPa, SE: 18.15 MPa, LP: 15.57 MPa. SM had significantly higher microtensile bond strength than 8E and PL (p < 0.05). but there was no significant differance between SE and PL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.81-88
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• 2002

A new pattern generator of BIST based on the pattern clustering is developed. The proposed technique embeds a pre-computed deterministic test set with low hardware overhead for test-per-clock environments. The test control logic is simple and can be synthesized automatically. Experimental results for the ISCAS benchmark circuits show that the effectiveness of the new pattern generator compared to the previous methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.84-91
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• 2009

A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1862-1863
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• 2007

Testing the analog/mixed-signal circuitry of a mixed-signal IC has become a difficult task. Offset error, gain error, Non-monotonic behavior, Differential Non-linearity(DNL) error, Integral Non-linearity(INL) error are important specifications used as test parameters for DAC. In this paper, we propose an efficient BIST structure for DAC testing. The proposed BIST adds the circuit which uses the capacitor and op-amp, and accomplishes a test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.526-531
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• 2003

Recently, many BIST(Built-in Self Test) schemes have been researched to reduce test time and hardware. But, most BIST schemes about pattern generation are for deterministic pattern generation. In this paper a new pseudo-random BIST scheme is provided to reduce the existing test hardware and keep a reasonable length of test time. Theoretical study demonstrates the possibility of the reduction of the hardware for pseudo-random test with some explanations and examples. Also the experimental results show that in the proposed test scheme the hardware for the pseudo-random test is much less than in the previous scheme and provide comparison of test time between the proposed scheme and the current one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.