• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.811-814
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• 1998

REcent research about current testing($\textrm{I}_{DDQ}$ testing) has been emphasizing that $\textrm{I}_{DDQ}$ testing in addition to the logical voltage testing is necessary to increase the fault coverage. The $\textrm{I}_{DDQ}$. testing can detect physical faults other than the classical stuck-at type fault, which affect reliability. One of the most critical issues in the $\textrm{I}_{DDQ}$ testing is to insert a built-in current sensor (BICS) that can detect abnormal static currents from the power supply or to the ground. This paper presents a new BICS for internal current testing for large CMOS logic circuits. The proposed BICS uses a single phase clock to minimize the hardware overhead. It detects faulty current flowing and converts it into a corresponding logic voltage level to make converts it into a corresponding logic voltage level to make it possible to use the conventional voltage testing techniqeus. By using current mirroring technique, the proposed BICS can work at very high speed. Because the proposed BICS almost does not affects normal operation of CUT(circuit under test), it can be used to a very large circuit without circuit partitioning. By altenating the operational modes, a circuit can be $\textrm{I}_{DDQ}$-tested as a kind of self-testing fashion by using the proposed BICS.

• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.56-61
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• 2013

Modern integrated circuits (ICs) are becoming an integrated parts of analog, digital, and radio frequency (RF) circuits. Testing these RF circuits on a chip is an important task, not only for fabrication quality control but also for tuning RF circuit elements to fit multi-standard wireless systems. In this paper, RF test circuits suitable for embedded testing are introduced: RF power detectors, power control circuits, directional couplers, and six-port reflectometers. Various types of embedded RF power detectors are reviewed. The conventional approach and our approach for the RF power control circuits are compared. Also, embedded tunable active directional couplers are presented. Then, six-port reflectometers for embedded RF testing are introduced including a 77-GHz six-port reflectometer circuit in a 130 nm process. This circuit demonstrates successful calibrated reflection coefficient simulation results for 37 well distributed samples in a Smith chart. The details including the theory, calibration, circuit design techniques, and simulations of the 77-GHz six-port reflectometer are presented in this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.63-70
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• 2004

This paper describes the link layer and physical layer of the Serial ATA which is the next generation for parallel ATA specification that defines data transfer between PC and peripheral storage devices. The link layer consists of CRC generation/error detection, 8b/10b decoding/encoding, primitive generation/detection block. For the physical layer, it includes CDR(Cock Data Recovery), transmission PLL, serializer/de-serializer. It also includes generation and receipt of OOB(Out-Of-Band) signal, impedance calibration, squelch circuit and comma detection/generation. Additionally, this chip includes TCB(Test Control Block) and BIST(Built-In Selt Test) block to ease debugging and verification. It is fabricated with 0.18${\mu}{\textrm}{m}$ standard CMOS cell library. All the function of the link layer operate properly. For the physical layer, all the blocks operate properly but the data transfer is limited to the 1.28Gbps. This is doe to the affection or parasitic elements and is verified with SPICE simulation.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1633-1638
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• 1998

In this paper we propose a generic BIST builder for the Embedded Multiple HAM modules in ASICs, The BlST circuitry is automatically generated according to the specification of the target RAM Modules and the applying test algorithms to them. The lJIST is designed using the TOP-DOWN technique and, thus, has the several advantages in the area of the selection of test algorithm, the development of the circuitry, and the reuse of the circuitry, In addition, we have modified the existing serial interiacing approach to obtain smaller additional BlST circuitry and higher fault coverage and better B1ST sharing of the target RAM Modules in ASICs.

• Korean Journal of Occupational Health Nursing
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• v.20 no.1
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• pp.1-13
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• 2011

Purpose: This study was conducted to compare the characteristics of organizational structure and occupational satisfaction among nurses in general hospital and small to medium-sized hospital and to investigate the affecting factors on their occupational satisfaction. Methods: The study was based on the cross-sectional descriptive survey. A self-report questionnaire was used to collect data from 343 nurses between June and July, 2010. Data were analyzed by ${\chi}^2$-test, t-test, ANOVA, Scheffe's test, Pearson's correlation coefficient, and multiple regression using the SPSS/WIN 14.0 program. Results: Hierarchical structure was dominant in general hospital whereas relationship was highly valued in small to medium-sized hospital. Occupational satisfaction was positively correlated with work environment built on relationship, innovation and tasks. Factors significantly influencing on occupational satisfaction in general hospital included innovative work environment, nurses' income and their health status ($R^2$=40.3%). For the small to medium-sized hospital, they included innovative work environment, satisfaction in life, tasks and professionalism ($R^2$=40.4%). Conclusion: Organizational structure, especially innovative work environment and relationship-oriented attitude had a significant influence on nurses' occupational satisfaction. Therefore, nursing administrators have to develop and consider organizational structure to improve occupational satisfaction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.30-37
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• 2006

This paper presents a modified scan cell architecture to reduce the power dissipation during testing. It not only eliminates switching activities in the combinational logic during scan shifting but also reduces switching activities in the scan chain during the time. Furthermore, it limits the transitions on capture cycles. It can be made for test-per-scan BIST and employed in both single scan style and multiple scan style. Experimental results demonstrate that the proposed structure achieves the same fault coverage with lower power consumption compared to other existing BIST schemes.

• The Journal of Advanced Prosthodontics
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• v.5 no.4
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• pp.479-484
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• 2013

PURPOSE. The aim of this study was to evaluate the effects of additional acid etching and curing mechanism (light-curing or self-curing) of a composite resin on the dentin bond strength and compatibility of one-step self-etching adhesives. MATERIALS AND METHODS. Sixteen human permanent molars were randomly divided into eight groups according to the adhesives used (All-Bond Universal: ABU, Clearfil S3 Bond: CS3), additional acid etching (additional acid etching performed: EO, no additional acid etching performed: EX), and composite resins (Filtek Z-250: Z250, Clearfil FII New Bond: CFNB). Group 1: ABU-EO-Z250, Group 2: ABU-EO-CFNB, Group 3: ABU-EX-Z250, Group 4: ABU-EX-CFNB, Group 5: CS3-EO-Z250, Group 6: CS3-EO-CFNB, Group 7: CS3-EX-Z250, Group 8: CS3-EX-CFNB. After bonding procedures, composite resins were built up on dentin surfaces. After 24-hour water storage, the teeth were sectioned to make 10 specimens for each group. The microtensile bond strength test was performed using a microtensile testing machine. The failure mode of the fractured specimens was examined by means of an optical microscope at ${\times}20$ magnification. The data was analyzed using a one-way ANOVA and Scheffe's post-hoc test (${\alpha}$=.05). RESULTS. Additional etching groups showed significantly higher values than the no additional etching group when using All-Bond Universal. The light-cured composite resin groups showed significantly higher values than the self-cured composite resin groups in the Clearfil S3 Bond. CONCLUSION. The additional acid etching is beneficial for the dentin bond strength when using low acidic one-step self-etch adhesives, and low acidic one-step self-etch adhesives are compatible with self-cured composite resin. The acidity of the one-step self-etch adhesives is an influencing factor in terms of the dentin bonding strength and incompatibility with a self-cured composite resin.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.284-292
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• 2008

The density of Memory has been increased by great challenge for memory technology; therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip(SoC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. We present a ARM processor-programmable built-in self-test(BIST) scheme suitable for embedded memory testing in the SoC environment. The proposed BIST circuit can be programmed vis an on-chip microprocessor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.24-33
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• 2002

For mixed signal circuits that integrate both analog and digital blocks onto the same chip, testing the mixed circuits has become the bottleneck. Since most of mixed signal circuits are functionally tested, mixed signal testing needs expensive automatic test equipments for test input generation and response acquisition. In this paper, a new efficient BIST is developed which can be used for mixed signal circuits. In the new BIST, only faults on embedded resistances, capacitances and its combinations are considered. To guarantee the quality of chips, the new BIST performs both voltage testing and phase testing. Using these two testing modes, all the faults are detected. In order to support this technique, the voltage detector and the phase detector are developed. Experimental results prove the efficiency of the new BIST.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.74-80
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• 2002

VLSI intergrated circuits like SOC(system on chip) often require a multi-clock design style for functional or performance reasons. The problems of the clock domain transition due to clock skew and clock ordering within a test cycle may result in wrong results. This paper describes a new BIST(Built-in Self Test) architecture for multi-clock systems. In the new scheme, a clock skew is eliminated by a multi-capture. Therfore, it is possible to perform at-speed test for both clock inter-domain and clock intra-domain.