• 센서학회지
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• 제13권4호
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• pp.277-281
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• 2004

$Hg_{1-x}Cd_{x}Te$ (MCT) was grown by hot wall epitaxy. Prior to the MCT growth, the CdTe (111) buffer layer was grown on the GaAs substrate at the temperature of $590^{\circ}C$ for 15 min. When the thickness of the CdTe buffer layer was $5{\mu}m$ or thicker, the full width at half maximum values obtained from the x-ray rocking curves were found to significantly decrease. After a good quality CdTe buffer layer was grown, the MCT epilayers were grown on the CdTe (111)/GaAs substrate at various temperatures in situ. The crystal quality for those epilayers was investigated by means of the x-ray rocking curves and the photocurrent experiment. The photoconductor characterization for the epilayers was also measured. The energy band gap of MCT was determined from the photocurrent measurement and the x composition rates from the temperature dependence of the energy band gap were turned out.

• Journal of Information Display
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• 제12권1호
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.261-262
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• 2006

High temperature superconducting coated conductor has multi-layer structure of protecting layer/superconducting layer/buffer layer/metallic substrate. The buffer layer consists of multi layer, and the architecture most widely used in RABiTS approach is $CeO_2$(cap layer)/YSZ(diffusion barrier layer)/$CeO_2$(seed layer). Multi-buffer layer deposition required many times and process. Therefore single buffer layer deposition study reduce 2G HTS manufacture efforts. Evaporation technique for single buffer deposition method is used for the $CeO_2$ layer. $CeO_2$ single buffer film could be achieved in the chamber. Detailed deposition conditions (temperature and partial gas pressure of deposition) were investigated for the rapid growth of high quality $CeO_2$ single buffer film.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 1999년도 제1회 학술대회논문집(KIASC 1st conference 99)
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• pp.189-193
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• 1999

An experimental study was carried out to improve the cooling capacity and performance of the pulse tube refrigerator. Three buffer pulse tube refrigerator was designed and fabricated, and the experimental apparatus was constructed. This paper presents operating process of three buffer pulse tube refrigerator and results obtained with the performance test. The cooldown characteristics and load characteristics are described. The lowest temperature measured in three pulse tube refrigerator was 88K and the cooling capacity at the optimum operating condition was 27W at 120K.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2001년도 추계연구발표회 논문개요집
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• pp.92-93
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• 2001

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.766-769
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• 2002

We have seen the effects of hole-injection buffer layer in organic light-emitting diodes using copper phthalocyanine(CuPc), poly(vinylcarbazole)(PVK), and Poly(3,4-ethylenedioxythiophene):poly(styrene-sulfonate)(PEDOT:PSS) in a device structure of ITO/buffer/TPD/$Alq_3$/Al. Polymer PVK and PEDOT:PSS buffer layer was made using spin casting method and the CuPc layer was made using thermal evaporation. Current-voltage characteristics, luminance-voltage characteristics and efficiency of device were measured at room temperature with a thickness variation of buffer layer. We have obtained an improvement of the external quantum efficiency by a factor of two, four, and two and half when the CuPc, PVK, and PEDOT:PSS buffer layer are used, respectively. The enhancement of the efficiency is attributed to the improved balance of holes and elelctrons due to the use of hole-injection buffer layer. The CuPc and PEDOT:PSS layer functions as a hole-injection supporter and the PVK layer as a hole-blocking one.

• 한국세라믹학회지
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• 제34권4호
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• pp.373-379
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• 1997

A study on the deposition and characterization of BaTiO3 thin films on MgO-buffered Si(100) substrates by sputtering was conducted. The MgO buffer layers were investigated as a function of deposition temperature. At lower substrate temperature, the MgO layers were not fully crystalline, but a crystallized MgO layer with (001) preferred orientation was obtained at the substrate temperature of $700^{\circ}C$. Partially (00ι) or (h00) textured BaTiO3 films were obtained on Si(100) with the MgO buffer layer grown at 700ι. While, randomly oriented BaTiO3 films with large-scale cracks on the surface were made without the MgO layer. The crystallographic orientation, morphology and electrical properties between the BaTiO3 films on Si with and without the MgO layer were compared using the BaTiO3 film on MgO(100) single crystal substrate as a reference system. Also the favorable role of the MgO layer as a buffer for growing of oriented BaTiO3 films on Si substrates was confirmed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1646-1648
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• 2000

This paper investigated structural and electrical properties of $Y_{2}O_3$ as a buffer layer of sin91r transistor FRAM (ferroelectric RAM). $Y_{2}O_3$ buffer layers were deposited at a low substrate temperature below 400$^{\circ}C$ and then RTA (rapid thermal anneal) treated. Investigated parameters are substrate temperature, $O_2$ partial pressure, post- annealing temperature, and suppression of interfacial $SiO_2$ layer generation. for a well-fabricated sample, we achieved that leakage current density ($J_{leak}$) in the order of $10^{-7}A/cm2$, breakdown electric field ($E_{br}$) about 2 MV/cm for $Y_{2}O_3$ film. Capacitance versus voltage analysis illustrated dielectric constants of 7.47. We successfully achieved an interface state density of $Y_{2}O_3$/Si as low as $8.72{\times}10^{10}cm^{-2}eV^{-1}$. The low interface states were obtained from very low lattice mismatch less than 1.75%.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.116-119
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• 2003

[ $Hg_{1-x}Cd_xTe$ ] (MCT) was grown by hot wall epitaxy method. Prior to the MCT growth, the CdTe (111) buffer layer was grown on the GaAs substrate at the temperature of 590 C for 15 min. When the thickness of the CdTe buffer layer was 5 m or thicker, the full width at half maximum values obtained from the x-ray rocking curves were found to significantly decrease. After a good quality CdTe buffer layer was grown, the MCT epilayers were grown on the CdTe (111) /GaAs substrate at various temperature in situ. The crystal quality for those epilayers was investigated by means of the x-ray rocking curves and the photocurrent experiment. The photoconductor characterization for the epilayers was also measured. The energy band gap of MCT was determined from the photocurrent measurement and the x composition rates from the temperature dependence of the energy band gap were turned out.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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• pp.392-396
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• 1999

Superconducting YBa$_2Cu_3O_{7-{\delta}}$(YBCO) thin films were grown on Hastelloy(Ni-Cr-Mo alloys) with CeO$_2$ buffer layer in-situ by pulsed laser deposition in a multi-target processing chamber. To apply superconducting property on power transmission line, we have deposited YBCO thin film on flexible metallic substrate. However, it is difficult to grow the YBCO films on flexible metallic substrates due to both interdiffusion problem between metallic substrate and superconducting overlayers and non-crystallization of YBCO on amorphous substrate. It is necessary to use a buffer layer to overcome the difficulties. We have chosen CeO$_2$ as a buffer layer which has cubic structure of 5.41 ${\AA}$ lattice parameter and only 0.2% of lattice mismatch with 3.82 ${\AA}$ of a-axis lattice parameter of YBCO on [110] direction of CeO$_2$ In order to enhance the crystallization of YBCO films on metallic substrates, we deposited CeO$_2$ buffer layers with varying temperature and 02 pressure. By XRD, it is observed that dominated film orientation is strongly depending on the deposition temperature of CeO$_2$ layer. The dominated orientation of CeO$_2$ buffer layer is changed from (200) to(111) by increasing the deposition temperature and this transition affects the crystallization of YBCO superconducting film on CeO$_2$ buffered Hastelloy.