• Korean Journal of Materials Research
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• v.30 no.11
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• pp.595-600
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• 2020

The photovoltaic properties of perovskite solar cells (PSCs) with a carbon electrode fabricated using different annealing processes are investigated. Perovskite formation (50 ℃, 60 min) using a hot-plate and an oven is carried out on cells with a glass/fluorine doped TiO₂/TiO₂/ZrO₂/carbon structure, and the photovoltaic properties of the PSCs are analyzed using a solar simulator. The microstructures of the PSCs are characterized using an optical microscope, a field emission scanning electron microscope, and an electron probe micro-analyzer (EPMA). Photovoltaic analysis shows that the energy conversion efficiency of the samples fabricated using the hot-plate and the oven processes are 2.08% and 6.90%, respectively. Based on the microstructure of the samples and the results of the EPMA, perovskite is formed locally on the carbon electrode surface as the γ-butyrolactone (GBL) solvent evaporates and moves to the top of the carbon electrode due to heat from the bottom of the sample during the hot plate process. When the oven process is used, perovskite forms evenly inside the carbon electrode, as the GBL solvent evaporates extremely slowly because heat is supplied from all directions. The importance of the even formation of perovskite inside the carbon electrode is emphasized, and the feasibility of oven annealing is confirmed for PSCs with carbon electrodes.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.178-180
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• 1993

The back bias effect on the breakdown voltage of SOI $p^+$-n diode is investigated. The breakdown voltage of the SOI $p^+$-n diode increases with the applied back bias. When the cathode electrode is used as a back bias, it is necessary to put the dielectric material between the Si-substrate and the bottom cathode electrode.

• Proceedings of the KIEE Conference
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• 2007.11a
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• pp.126-127
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• 2007

In this study, the fabrication technique of a plannar field emission structure with DLC were studied Electric properties of carbon film on silicon substrate in methanol solution was carried out with various current density, solution temperature and electrode spacing between anode and cathode. The DLC film deposited on the Si substrate, plannar $SiO_2$ was obtained due to the shape of bottom electrode.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.09a
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• pp.102-105
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• 2005

In this study Al electrode for OLED was deposited by FTS(Facing Targets Sputtering) system which can deposit thin films with low substrate damage. The Al thin films were deposited on the cell (LiF/EML/HTL/Bottom electrode) as a function of working gas such as Ar, Kr or mixed gas. Also Al thin films were prepared with working gas pressure (1, 6 mTorr ). The film thickness and I-V curve of Al/cell were evaluated by $\alpha$-step and semiconductor parameter (HP4156A) measurement.

• Journal of Advanced Marine Engineering and Technology
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• v.32 no.1
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• pp.162-168
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• 2008

In this paper, we analyzed the heat transfer phenomenon and the reset current variation of PRAM device with thickness of phase change material using the 3-D finite element analysis tool. From the simulation, Joule's heat was generated at the contact surface of phase change material and bottom electrode of PRAM. As the thickness of phase change material was decreased, the reset current was highly increased. In case thickness of phase change material thin film was $200\;{\AA}$, heat increased through top electrode and reset current caused by phase transition highly increased. And as thermal conductivity of top electrode decreased, temperature of unit memory cell was increased.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.440-440
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• 2012

The optical characteristics of transparent electrode with various kind of materials and thickness to be used for organic photovoltaic cells were studied by simulation methodology. It demonstrated that the transmittance varies with the kinds of materials, the number of layers and change in the thickness of each layer. In the case of the structure composed of dielectric/Ag/dielectric, optimized transmittance was higher than 90% at 550 nm and the thickness of the Ag layer was ~10nm. Top and bottom dielectric materials can be changed with different refractive index and extinction coefficient. The relation between the optical transmittance of device and transparent electrode with different refractive indices was discussed as well. By processing numerical simulations, an optimized optical transmittance can be obtained by tunning the thickness and materials of transparent electrode.

• Korean Journal of Materials Research
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• v.13 no.2
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• pp.69-73
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• 2003

In this work, $IrO_2$thin films as bottom electrode of ferroelectric capacitors were deposited and characterized. The $IrO_2$films deposited in the conditions of 25, 40 and 50% oxygen ambient by sputtering method were annealed at 600, 700 and $800^{\circ}C$, respectively. It was found that the crystallinity and the surface morphology of $IrO_2$films affected the surface properties and electrical properties of SBT thin films prepared by the MOD method. With increasing temperature, the crystallinity and the roughness of $IrO_2$films were also increasing. This increasing of roughness degraded the surface properties and electrical properties of SBT films. We found an optimum condition of $IrO_2$films as bottom electrode for ferroelectric capacitor at 50% oxygen ambient and $600^{\circ}C$ annealing temperature. Electrical characterizations were performed by using$ IrO_2$bottom electrodes grown at an optimum conditions. The remanent polarization ($P_{r}$) of the Pt/SBT/$IrO_2$/$SiO_2$/Si structure was 2.75 $\mu$C/$\textrm{cm}^2$ at an applied voltage of 3 V. The leakage current density was $1.06${\times}$10^{-3}$ A/$\textrm{cm}^2$ at an applied voltage of 3 V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.4
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• pp.281-285
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• 2020

Oxide semiconductor devices have become increasingly important because of their high mobility and good uniformity. The channel length of oxide semiconductor thin film transistors (TFTs) also shrinks as the display resolution increases. It is well known that reducing the channel length of a TFT is detrimental to the current saturation because of drain-induced barrier lowering, as well as the movement of the pinch-off point. In an organic light-emitting diode (OLED), the lack of current saturation in the driving TFT creates a major problem in the control of OLED current. To obtain improved current saturation in short channels, we fabricated indium gallium zinc oxide (IGZO) TFTs with single gate and double gate structures, and evaluated the electrical characteristics of both devices. For the double gate structure, we connected the bottom gate electrode to the source electrode, so that the electric potential of the bottom gate was fixed to that of the source. We denote the double gate structure with the bottom gate fixed at the source potential as the BGFP (bottom gate with fixed potential) structure. For the BGFP TFT, the current saturation, as determined by the output characteristics, is better than that of the conventional single gate TFT. This is because the change in the source side potential barrier by the drain field has been suppressed.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.357-358
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• 2013

The non-linear characteristics of ON states are important for the application to the high density cross-point memory industry because the sneak current in neighbor cells occurred during reading, erasing, and writing process. Kw of above 20 in ON states, which is the writing current @ Vwrite/the current @ 1/2Vwrite, was required in cross-point ReRAM memory industry. The high current density non-linear IV curve of ZnSe selector was shown and the ALD HfO2 switching device has the linear properties of ON states and the compliance current of 100 uA. To evaluate the performance of the selection device, we connected itto HfO2 switching device in series. The bottom electrode of the selection device was connected to the top electrode of the RRAM. All of the bias was applied with respect to the top electrode of the selection device, whereas the bottom electrode of the RRAM was grounded. In the cross-point application, 1/2Vwrite and -1/2Vwrite were applied to the word-line and bit-line, respectively, which were connected to the selected cell, and a zero bias was applied to the unselected word-lines and bit-lines. The current @ 1/2Vwrite of the unselected cells was blocked by the selection device, thus eliminating the sneak path and obtaining a writing voltage margin. Using this method, the writing voltage margin was analyzed on the basis of the memory size.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.6
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• pp.68-74
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• 2011

The touch or step voltages which exist in the vicinity of a grounding electrode are closely related to the earth structure and resistivity and the ground current. The grounding design approach is required to determine the grounding electrode location where the hazardous voltages are minimized. In this paper, in order to propose a method of mitigating the electric shock hazards caused by the ground surface potential rise in the vicinity of a counterpoise, the hazards relevant to touch voltage were evaluated as a function of the soil resistivity ratio $\rho_2/\rho_1$ for several practical values of two-layer earth structures. The touch voltage and current on the ground surface just above the test electrode are calculated with CDEGS program. As a consequence, it was found that burying a grounding electrode in the soil with low resistivity is effective to reduce the electric shock hazards. In the case that the bottom layer soil where a counterpoise is buried has lower resistivity than the upper layer soil, when the upper layer soil resistivity is increased, the surface potential is slightly raised, but the current through the human body is reduced with increasing the upper layer soil resistivity because of the greater contact resistance between the earth surface and the feet. The electric shock hazard in the vicinity of grounding electrodes is closely related to soil structure and resistivity and are reduced with increasing the ration of the upper layer resistivity to the bottom layer resistivity in two-layer soil.