• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1482-1490
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• 2001

디지털 통신 시스템 및 신호처리 회로의 핵심 연산블록으로 사용될 수 있는 복소수 승산기 코어의 파라미터화된 소프트 IP (Intellectual Property)를 설계하였다. 승산기는 응용분야에 따라 요구되는 비트 수가 매우 다양하므로, 승산기 코어 IP는 비트 수를 파라미터화하여 설계하는 것이 필요하다. 본 논문에서는 복소수 승산기의 비트 수를 파라미터화 함으로써 사용자의 필요에 따라 승수와 피승수를 8-b∼24-b 범위에서 2-b 단위로 선택하여 사용할 수 있도록 하였으며, GUI 환경의 코어 생성기 PCMUL_GEN는 지정된 비트 크기를 갖는 복소수 승산기의 VHDL 모델을 생성한다. 복소수 승산기 코어 IP는 redundant binary (RB) 수치계와 본 논문에서 제안하는 새로운 radix-4 Booth 인코딩/디코딩 회로를 적용하여 설계되었으며, 이를 통해 기존의 방식보다 단순화된 내부 구조와 고속/저전력 특성을 갖는다. 설계된 IP는 Xilinx FPGA로 구현하여 기능을 검증하였다.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.778-780
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• 1999

Arithmetic unit speed depends strongly on the algorithms employed to realize the basic arithmetic operations.(add, subtract multiply, and divide) and on the logic design. Recent advances in VLSI have increased the feasibility of hardware implementation of floating point arithmetic units and microprocessors require a powerful floating-point processing unit as a standard option. This paper describes the design of floating-point multiplier for IEEE 754-1985 Single-Precision operation. Booth encoding algorithm method to reduce partial products and a Wallace tree of 4-2 CSA is adopted in fraction multiplication part to generate the $32{\times}32$ single-precision product. New scheme of rounding and sticky-bit generation is adopted to reduce area and timing. Also there is a true sign generator in this design. This multiplier have been implemented in a ALTERA FLEX EPF10K70RC240-4.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.521-522
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• 2006

This paper calculates co-generation generating capacity for the electric supply and demand. CHP is applied to SCM(Screening Curve Method) to calculate CHP generating capacity On the other hand, small co-generation is applied to potential area conversing small co-generation generating capacity considering economic analysis and useful life. these methods executed project scheduled to construction plan. Accordingly, EES(Expected Energy Served), Fuel type consumption and CO2 effects is analyzed by Booth-Baleriaux and data

• Proceedings of the KWS Conference
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• 2002.10a
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• pp.169-175
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• 2002

World demand for natural gas has generated the need for many new land transmission pipelines to be installed in the next decade or so. Although mechanized gas metal arc welding is well developed, there are opportunities for cost savings by using alternative welding processes. Hybrid Nd:YAG laser - gas metal arc welding enables fibre optic delivery of the laser energy to a robotic welding head to be combined with the addition of extra energy and a consumable to produce good quality, deep penetration welds in a single pass. The present paper describes initial procedure development to optimize the laser and gas metal arc welding parameters for making joints in pipeline steel. Satisfactory joint quality was obtained and it is intended to develop the process to prototype field trials.

• Journal of Magnetics
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• v.1 no.2
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• pp.82-85
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• 1996

Magnetic properties and microstructures of melt spun misch metal-ferroboron alloys were investigated. The major phase is the tetragonal (rare earth)$_2Fe_{14}B$ phase. Magnetic properties showed coercivity of 5.6 kOe, remanence of 7.85 kG, and so energy product 8.9 MGOe. Microsturctures in optimum properties showed that matrix was composed of Ce-rich phase while second phase La-rich-oxygen phase with less amount of Fe element than matrix, and triple junction with La-rich phase contrary to matrix.

• Journal of Korean Association for Spatial Structures
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• v.20 no.3
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• pp.35-42
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• 2020

The purpose of this study is to develop precast concrete modules that can be used as a booth and a single-story building with a large space. This precast concrete module is originally designed to have a hexagonal facade when the upper and lower parts, which are symmetrical about horizontal connection line, are combined. A structural design was conducted to ensure structural safety of these precast concrete modules and to extend the slope of the inclined members as far as possible. Then the finite element analysis was performed to estimate the lateral and vertical deflection of complete precast concrete modular structures. And to verify the structural safety of these precast concrete modules, weight loading tests were conducted on the upper and lower modules respectively.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.285-288
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• 2002

In this paper, a new structure of 1024-bit high-speed RSA cryptosystem has been proposed and implemented in hardware to increase the operation speed and enhance the variable-length operation in the plain text. The proposed algorithm applied a radix-4 Booth algorithm and CSA(Carry Save Adder) to the Montgomery algorithm for modular multiplication As the results from implementation, the clock period was approached to one delay of a full adder and the operation speed was 150MHz. The total amount of hardware was about 195k gates. The cryptosystem operates as the effective length of the inputted modulus number, which makes variable length encryption rather than the fixed-length one. Therefore, a high-speed variable-length RSA cryptosystem could be implemented.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.173-176
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• 2002

This paper is about a high-speed MAC (multiplier and accumulator) design applying radix-4 and radix-8 Booth's algorithm at the same time. The optimized hybrid radix design for high speed MAC has taken advantage of both a radix-4 and a radix-8 architectures. A radix-4 architecture meets high-speed, but it takes much more power and chip area than a radix-8 architecture. A radix-8 architecture needs less power and chip area than the other, but it has a bottleneck of generating three times the multiplicand problem. An optimized hybrid architecture performs the radix-4 multiplication partially in parallel with the generation of three times the multiplicand for use of the radix-8 multiplication. It reduces the concerned bit width of multiplier in radix-8 multiplication.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.27-35
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• 1997

In this paper, we propose a new scheme for the generation of partial products for VLSI fast parallel multiplier. It adopts a new encoding method which halves the number of partial products using 2x2 submultipliers and rearrangement of primitive partial products. The true 4-input CSA can be achieved with appropriate rearrangement of primitive partial products out of 2x2 submultipliers using the newly proposed theorem on binary number system. A 16bit x 16bit multiplier has been desinged using the proposed method and simulated to prove that the method has comparable speed and area compared to booth's encoding method. Much smaller and faster multiplier could be obtained with far optimization. The proposed scheme can be easily extended to multipliers with inputs of higher resolutions.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.914-917
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• 1999

The paper describes a 17 $\times$ 17-b multiplier using the Radix-4 Booth’s algorithm. which is suitable for 32-bit RISC/DSP microprocessors. To minimize design area and achieve improved speed, a 2-stage pipeline structure is adopted to achieve high clock frequency. Each part of circuit is modeled and optimized at the transistor level, verification of functionality and timing is performed using HSPICE simulations. After modeling and validating the circuit at transistor level, we lay it out in a 0.35 ${\mu}{\textrm}{m}$ 1-poly 4-metal CMOS technology and perform LVS test to compare the layout with the schematic. The simulation results show that maximum frequency is 330MHz under worst operating conditions at 55$^{\circ}C$ , 3V, The post simulation after layout results shows 187MHz under worst case conditions. It contains 9, 115 transistors and the area of layout is 0.72mm by 0.97mm.