• Journal of Power Electronics
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• 제4권1호
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• pp.18-27
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• 2004

The output storage capacitor of the PFC converters is commonly designed for the selected hold-up time or the allowed output ripple voltage percentage. Nevertheless, this output capacitor is a main contribution factor to the PFC system stability. Moreover, seeking for a minimum output storage capacitor that assures the PFC desired operation under all condition, and providing the advantage of a small size and low cost is the main interesting target for engineering. Therefore, in this issue the design steps of the PFC converter have been discussed depending on three choices, output ripple, hold-up time, and stability. It is cleared that any design must take the minimum required storage capacitor for stability prospective as step-l in deign, then apply for any other specification like hold-up time or ripple percentage.

• Journal of Power Electronics
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• 제7권4호
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• pp.328-335
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• 2007

A conventional Single-Stage Power-Factor-Correction (PFC) AC/DC converter has a link capacitor voltage problem under high line input and low load conditions. In this paper, this problem is analyzed by using the voltage conversion ratio of the DC/DC conversion cell. By applying this analysis, a new Single-Stage PFC AC/DC converter with a boost PFC cell integrated with a Voltage-Doubler Rectified Asymmetrical Half-Bridge (VDRAHB) is proposed. The proposed converter features good power factor correction, low current harmonic distortions, tight output regulations and low voltage of the link capacitor. An 85W prototype was implemented to show that it meets harmonic requirements and standards satisfactorily with near unity power factor and high efficiency over universal input.

• 전력전자학회논문지
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• 제22권6호
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• pp.527-534
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• 2017

This paper proposes a new DC link voltage controller for a single-phase power factor correction (PFC) boost converter. The load current of the PFC boost converter affects the capacitor current, whereas the load current changes the output voltage. However, previous works that compensate output current have failed to consider the relationship between load current and duty. Thus, they also fail to maintain a constant output voltage if the load fluctuates under the conditions of a non-rated input voltage. By considering the duty in the load current compensation, the proposed method improves the load transient response regardless of the input voltage. To demonstrate its effectiveness, the proposed method is compared with other control methods by conducting PSM simulations and experiments under a rapidly changing load.

• Journal of Power Electronics
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• 제15권2호
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• pp.356-365
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• 2015

This paper presents a new single phase front-end ac-dc bridgeless power factor correction (PFC) rectifier topology. The proposed converter achieves a high efficiency over a wide range of input and output voltages, a high power factor, low line current harmonics and both step up and step down voltage conversions. This topology is based on a non-inverting buck-boost (Zeta) converter. In this approach, the input diode bridge is removed and a maximum of one diode conducts in a complete switching period. This reduces the conduction losses and the thermal stresses on the switches when compare to existing PFC topologies. Inherent power factor correction is achieved by operating the converter in the discontinuous conduction mode (DCM) which leads to a simplified control circuit. The characteristics of the proposed design, principles of operation, steady state operation analysis, and control structure are described in this paper. An experimental prototype has been built to demonstrate the feasibility of the new converter. Simulation and experimental results are provided to verify the improved power quality at the AC mains and the lower conduction losses of the converter.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권9호
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• pp.590-597
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• 2000

Design of single state AC-DC converter with high power factor for low level applications is proposed. The proposed converter is obtained from the integration of a buck-boost converter and the half-bridge DC-DC converter. This converter gives the good power factor correction low line current harmonic distortions and tight output voltage regulations. This converter also has a high efficiency by employing an soft switching method and synchronous rectifier. The modelling and detailed analysis for the proposed converter are performed. To verify the performance of the proposed converter a 100W converter has been designed

• 전력전자학회논문지
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• 제4권1호
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• pp.91-98
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• 1999

본 논문에서는 역률개선용 단일 스위치 부스트 플라이백 결합형 ZCS quasi-resonant converter(QRC)를 제안한다. 제안된 컨버터는 입력전류를 불연속 모드로 동작시켜 역률을 개선하며 입력전류의 zero-crossing-point에서의 왜곡을 개선함으로써 고조파를 감소시켜 역률을 향상시켰으며 좋은 출력전압의 regulation 성능을 가지고 있다. 그리고 체계적인 설계를 위하여 설계식을 제안하였으며 제안된 설계식을 통하여 프로토타입 컨버터를 설계하였다. 실험결과 효율은 약 86%, 역률은 약 0.985이상을 얻었다. 따라서 본 컨버터는 스위칭 주파수가 수백 kHz이상이고 높은 regulation성능을 요구하는 낮은 전압의 소용량 컨버터에 적합하다.

• Journal of Power Electronics
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• 제12권3호
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• pp.377-386
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• 2012

An interleaved bridgeless buck-boost AC/DC converter is presented in this paper to achieve the characteristics of low conduction loss, a high power factor and low harmonic and ripple currents. There are only two power semiconductors in the line current path instead of the three power semiconductors in a conventional boost AC/DC converter. A buck-boost converter operated in the boundary conduction mode (BCM) is adopted to control the active switches to achieve the following characteristics: no diode reverse recovery problem, zero current switching (ZCS) turn-off of the rectifier diodes, ZCS turn-on of the power switches, and a low DC bus voltage to reduce the voltage stress of the MOSFETs in the second DC/DC converter. Interleaved pulse-width modulation (PWM) is used to control the switches such that the input and output ripple currents are reduced such that the output capacitance can be reduced. The voltage doubler topology is adopted to double the output voltage in order to extend the useable energy of the capacitor when the line voltage is off. The circuit configuration, principle operation, system analysis, and a design example are discussed and presented in detail. Finally, experiments on a 500W prototype are provided to demonstrate the performance of the proposed converter.

• Journal of Power Electronics
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• 제14권5호
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• pp.890-898
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• 2014

Critical conduction mode boost power factor correction converters operating at the boundary of continuous conduction mode and discontinuous conduction mode have been widely used for power applications lower than 300W. This paper proposes an enhanced variable on-time control method for the critical conduction mode boost PFC converter to improve the total harmonic distortion characteristic. The inductor current, which varies according to the input voltage, is analyzed in detail and the optimal on-time is obtained to minimize the total harmonic distortion with a digital controller using a TMS320F28335. The switch on-time varies according to the input voltage based on the computed optimal on-time. The performance of the proposed control method is verified by a 100W PFC converter. It is shown that the optimized on-time reduces the total harmonic distortion about 52% (from 10.48% to 5.5%) at 220V when compared to the variable on-time control method.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.149-153
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• 1998

In this paper A switched mode AC/DC three phase boost converter with high power factor and sinusoidal input current waveform is analyzed and simulated. The proposed converter retain high power factor and sinusoidal input current waveform even under electric arc welder load. It is shown that experimental result and simulation waveform yield a sinusoidal input current waveform at high power factor.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.224-225
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• 2012

When Power Factor Correction(PFC) boost converter is designed for the universal input range, unwanted burst operation can be found at high line and light load. This operation may cause an audible noise from the boost inductor or sensitive flicker for human eye can be found in case of the display application. In order to solve this difficulty, this paper proposes the new control range compensation method and shows the effectiveness than the conventional method thru the experimental result.