• Proceedings of the KIEE Conference
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• 2000.11d
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• pp.778-780
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• 2000

The 74181 is arithmetic logic units(ALU)/function generator. This circuit performs 16 binary arithmetic operations on two 4-bit words. And a full carry look-ahead scheme is made available in this device. The 74181 can also be utilized as a comparator. This circuit has been also designed to provide 16 possible functions of two Boolean variables without the use of external circuitry. This paper analyzes the function of the logic and the implementation adopted in the design of 74181. The understanding of the logic characteristics of this chip enables us to improve future applications.

• Journal of the Chungcheong Mathematical Society
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• v.28 no.2
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• pp.331-343
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• 2015

Invertible transformations over n-bit words are essential ingredients in many cryptographic constructions. When n is large such invertible transformations are usually represented as a composition of simpler operations such as linear functions, S-P networks, Feistel structures and T-functions. Among them we study T-functions which are probably invertible transformations and are very useful in stream ciphers. In this paper we study the number of single cycle T-functions satisfying some conditions and characterize single cycle T-functions on $(\mathbb{Z}_2)^n$ generated by some elements in $(\mathbb{Z}_2)^{n-1}$.

• ETRI Journal
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• v.34 no.5
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• pp.795-798
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• 2012

This letter proposes a new low-complexity motion estimation method. The proposed method classifies various nonmatching pixel pairs into several categories and assigns an appropriate weight for each category in the matching stage. As a result, it can significantly improve performance compared to that of the conventional methods by adding only one 1-bit addition and two Boolean operations per pixel.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.616-619
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• 2002

The z-map structure is widely used for NC tool path verification as it is very simple and fast in calculation of Boolean operations. However, if the number of the x-y grid points in a z-map is increased to enhance its accuracy, the computation time for NC verification increases rapidly. To reduce this computation time, we proposed a NC verification method using 3-D graphic acceleration hardwares. In this method, the z-map of the resultant workpiece machined by a NC program is obtained by rendering tool swept volumes along tool pathos and reading the depth buffer of the graphic card. The experimental results show that this hardware-based method is faster than the conventional software-based method.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.6
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• pp.181-186
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• 2007

UBM (Under Bump Metallurgy) of flip chip assemblies consists of several layers such as the solder wetting, the diffusion barrier, and the adhesion layers. In addition, IMC layers are formed between the solder wetting layers (e.g. Cu, Ni) and the solder. The primary failure mechanism of the solder joints in flip chips is widely known as the fatigue failure caused by thermal fatigues or electromigration damages. Sometimes, the premature brittle failure occurs in the IMC layers. However, these phenomena have thus far been viewed from only experimental investigations. In this sense, this paper presents a method for solid modeling of IMC layers in flip chip assemblies, thus providing a pre-processing tool for finite element analysis to simulate the IMC failure mechanism. The proposed modeling method is CSG-based and can also be applied to the modeling of UBM structure in flip chip assemblies. This is done by performing Boolean operations according to the actual sequences of fabrication processes

• Journal of the Korea Computer Graphics Society
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• v.3 no.2
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• pp.77-84
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• 1997

Solid modeling refers to techniques for unambiguous representations of three- dimensional objects. The most widely used techniques for solid modeling have been Constructive Solid Geometry (CSG) and Boundary Representation (BRep). Contemporary solid modeling systems typically support both representations, and bilateral conversions between CSG and BRep are essential. However, computing a CSG from a BRep is largely an open problem. This paper presents 3D geometric reasoning algorithms for converting a BRep into a special CSG, called Destructive Solid Geometry (DSG) whose Boolean operations are all subtractions. The major application area of BRep-to-DSG conversion is feature recognition, which is essential for integrating CAD and CAM.

• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.6
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• pp.1064-1074
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• 1992

Eliminating the under-cut caused by interference between a mold and a product in designing a mold for in jection molding processes is a very important problem. In general, the under-cut problem can be avoided by side cores which are the principal members of a mold assembly. In this research, a procedure has been developed by which the side cores and the corresponding core and cavity plates of a mold are generated after identifying the mold faces preventing product faces from moving while being discharged. The characteristic features of the procedure suggested in this paper are as follows. One is that the interference faces between the product and the mold are derived only from the core plate(or cavity plate) alone without considering the product together. The other is that the algorithm in the designing of side cores and modifying molds, is very efficient because it uses Euler operations instead of Boolean operations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.305-311
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• 2010

iATA (Internet Advanced Technology Attachment) is a block-level protocol developed to transfer ATA commands over TCP/IP network, as an alternative network storage solution to address insufficient storage problem in mobile devices. This paper employs RAID5 distributed storage servers concept into iATA, in which the idea behind is to combine several machines with relatively inexpensive disk drives into a server array that works as a single virtual storage device, thus increasing the reliability and speed of operations. In the case of one machine failed, the server array will not destroy immediately but able to function in a degradation mode. Meanwhile, information can be easily recovered by using boolean exclusive OR (XOR) logical function with the bit information on the remaining machines. We perform I/O measurement and benchmark tool result indicates that additional fault tolerance feature does not delay read/write operations with reasonable file size ranged in 4KB-2MB, yet higher data integrity objective is achieved.

• Korean Journal of Computational Design and Engineering
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• v.10 no.1
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• pp.27-39
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• 2005

Implicit surfaces are geometric shapes which are defined by implicit functions and exist in three-dimensional space. Recently, implicit surfaces have received much attention in solid modeling applications because they are easy to represent the location of points and to use boolean operations. However, it is difficult to chart points on implicit surfaces for rendering. As efficient rendering method of implicit surfaces, the original Adaptively Sampled Distance Fields (ADFs) $method^{[1]}$ is to use sampled distance fields which subdivide the three dimensional space of implicit surfaces into many cells with high sampling rates in regions where the distance field contains fine detail and low sampling rates where the field varies smoothly. In this paper, in order to maintain the sharp features efficiently with small number of cells, an extended ADFs method is proposed, applying the Dual/Primal mesh optimization $method^{[2]}$ to the original ADFs method. The Dual/Primal mesh optimization method maintains sharp features, moving the vertices to tangent plane of implicit surfaces and reconstructing the vertices by applying a curvature-weighted factor. The proposed extended ADFs method is applied to several examples of implicit surfaces to evaluate the efficiency of the rendering performance.

• Journal of Computational Design and Engineering
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• v.3 no.2
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• pp.151-160
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• 2016

Cutter-workpiece engagement (CWE) is the instantaneous contact geometry between the cutter and the in-process workpiece during machining. It plays an important role in machining process simulation and directly affects the calculation of the predicted cutting forces and torques. The difficulty and challenge of CWE determination come from the complexity due to the changing geometry of in-process workpiece and the curved tool path of cutter movement, especially for multi-axis milling. This paper presents a new method to determine the CWE for general milling processes. To fulfill the requirement of generality, which means for any cutter type, any in-process workpiece shape, and any tool path even with self-intersections, all the associated geometries are to be modeled as triangle meshes. The involved triangle-to-triangle intersection calculations are carried out by an effective method in order to realize the multiple subtraction Boolean operations between the tool and the workpiece mesh models and to determine the CWE. The presented method has been validated by a series of case studies of increasing machining complexity to demonstrate its applicability to general milling processes.