• Journal of the Microelectronics and Packaging Society
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• v.10 no.4
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• pp.1-8
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• 2003

Thermo-mechanical behavior of a ceramic ball grid array (CBGA) package assembly are characterized by high sensitive moire interferometry. Moir fringe patterns are recorded and analyzed at various temperatures in a temperature cycle. Thermal-history dependent analyses of global and local deformations are presented, and bending deformation (warpage) of the package and shear strain in the rightmost solder ball are discussed. A significant non-linear global behavior is documented due to stress relaxation at high temperature. Analysis of the solder interconnections reveals that inelastic deformation accumulates on only eutectic solder fillet region at high temperatures.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.138-141
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• 2002

There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.17-26
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• 2010

Pb-Sn solder is rapidly being replaced by lead-free solder for board-level interconnection in microelectronic package assemblies due to the environmental protection requirement. There is a general lack of mechanical reliability information available on the lead-free solder. In this study, thermo-mechanical behaviors of wire-bond plastic ball grid array (WB-PBGA) package assemblies are characterized by high-sensitivity moire interferometry. Experiments are conducted for two types of WB-PBGA packages that have Pb-Sn solder and lead-free solder as joint interconnections. Using real-time moire setup, fringe patterns are recorded and analyzed for several temperatures. Bending deformations of the assemblies and average strains of the solder balls are investigated and compared for the two type of WB-PBGA package assemblies. Results show that shear strain in #3 solder ball located near the chip shadow boundary is dominant for the failure of the package with Pb-Sn solder, while normal strain in #7 most outer solder ball is dominant for that with lead-free solder. It is also shown that the package with lead-free solder has much larger bending deformation and 10% larger maximum effective strain than the package with Pb-Sn solder at same temperature level.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.1
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• pp.69-74
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• 2015

With difficulties during the cleaning of reflow flux residues due to the decrease of the part size and interconnection pitch in the advanced electronic devices, the need for the no-clean solder paste is increasing. In this study, an epoxy curable solder paste was made with SAC305 solder powder and the curable flux of which the main ingredient is epoxy resin and its reflow solderability, flux residue corrosivity and solder joint mechanical properties was investigated with comparison to the commercial rosin type solder paste. The fillet shape of the cured product around the reflowed solder joint revealed that the curing reaction occurred following the fluxing reaction and solder joint formation. The copper plate solderability test result also revealed that the wettability of the epoxy curable solder paste was comparable to those of the commercial rosin type solder pastes. In the highly accelerated temperature and humidity test, the cured product residue of the curable solder paste showed no corrosion of copper plate. From FT-IR analysis, it was considered to be resulted from the formation of tight bond through epoxy curing reaction. Ball shear, ball pull and die shear tests revealed that the adhesive bonding was formed with the solder surface and the increase of die shear strength of about 15~40% was achieved. It was considered that the epoxy curable solder paste could contribute to the improvement of the package reliability as well as the removal of the flux residue cleaning process.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.77-86
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• 2008

The reliability of leaded and lead-free solders of BGA type packages on a printed circuit board was investigated by employing the standard drop test and 4-point bending test. Tested solder joints were examined by optical microscopy to identify associated failure mode. Three-dimensional finite element analysis(FEM) with ANSYS Workbench v.11 was carried out to understand the mechanical behavior of solder joints under the influence of bending or drop impact. The results of numerical analysis are in good agreement with those obtained by experiments. Packages in the center of the PCB experienced higher stress than those in the perimeter of the PCB. The solder joints located in the outermost comer of the package suffered from higher stress than those located in center region. In both drop and bending impact tests, the lead-free solder showed better performances than the leaded solders. The numerical analysis results indicated that stress and strain behavior of solder joint were dependent on various effective parameters.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.