• Journal of Digital Contents Society
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• v.15 no.4
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• pp.481-489
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• 2014

In this paper, the automatic standby power blocking socket outlet to reduce standby power by blocking power threshold is implemented. Where, the standby power means a flowing power when a disused power electronic is plugged into the socket outlet. The proposed socket outlet can cut off the standby power by establishing a proper block power threshold electronic device according to each electronic device because it can monitor the amount of power through the smart machines such as the real-time PC or mobile phone and directly control the blocking power threshold. The software is implemented by using Visual Studio software, code vision and SN8 C studio, and the hardware is embodied in ATmega128, SN8F27E93S, USB to UART, and relay etc. Through the simulation, we find that the standby power of the proposed method is similar to that of the conventional method in case of the cellular phone but the standby power of the proposed method is much less than that of the conventional method in case of the computer, air conditioning, and set-top box. Therefore, it is proved that the proposed socket outlet has a superior performance in terms of the standby power.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.14-15
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• 2009

Insulated Gate Bipolar Transistor(IGBTs) are widely used in power device industry. However, to improve the breakdown voltage, IGBTs are suffered from increasing on-state voltage drop due to structural design. In this paper, the new structure is proposed to solve this problem. The proposed structure has double p-floating layer inserted in n-drift layer. The p-floating layers improve the breakdown voltage compared to conventional IGBT without change of other electrical characteristics such as on-state voltage drop and threshold voltage. this is because the p-floating layers expand electric field distribution at blocking state. A electrical characteristic of proposed structure is analyzed by using simulators such as TSUPREM and MEDICI. As a result, on-state voltage drop and threshold voltage are same to a conventional TIGBT, but breakdown voltage is improved to 16%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.350-350
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• 2010

Silicon carbide (SiC), one of the well known wide band gap semiconductors, shows high thermal conductivities, chemical inertness and breakdown energies. The design of normally-off 4H-SiC VJFETs [1] has been reported and 4H-SiC VJFETs with different lateral JFET channel opening dimensions have been studied [2]. In this work, 4H-SiC based VJFETs has been designed using the device simulator (ATLAS, Silvaco Data System, Inc). We varied the n-epi layer thickness (from $6\;{\mu}m$ to $10\;{\mu}m$) and the channel width (from $0.9\;{\mu}m$ to $1.2\;{\mu}m$), and investigated the static characteristics as blocking voltages, threshold voltages, on-resistances. We have shown that silicon carbide JFET structures of highly intensified blocking voltages with optimized figures of merit can thus be achieved by adjusting the epi layer thickness and channel width.

• Proceedings of the KIEE Conference
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• 2002.11b
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• pp.274-276
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• 2002

This paper proposes a current differential relaying algorithm for power transformers using the third difference function of a differential current. The algorithm observes the instants when the wave-shape of the differential current is changed due to the change of the magnetization inductance. If the value of the third difference is bigger than the threshold, the output of a current differential relay is blocked for a cycle. In the cases of magnetic inrush and overexcitation, the blocking signal is maintained: however, for internal faults, reset in a cycle. The test results clearly show that the algorithm successfully distinguishes internal faults from magnetizing inrush.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.831-837
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• 2002

Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3A
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• pp.129-139
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• 2003

CAC is a very important issue in CDMA system in order to protect the required QoS(quality of service) and increase the system's capacity. In this paper, we proposed and analyzed a call admission control scheme using multiple thresholds, which can provide quick processing time and better performance. There are two effective thresholds used to decide call admission. One is the number of active users, and the other is the signal to interference ratio(SIR). If the threshold of active users are lower than the low number of users threshold, we accept the new call without any other conditions. Otherwise, we check the current SIR to guarantee the quality of our service. System then accepts the new call when the SIR satisfies system requirement. Otherwise, the call will be rejected. Multiple threshold schemes are investigated and their performance is compared with the number of user and power based CAC's. simulation results are provided to evaluate the performance.