• Title/Summary/Keyword: Block mapping

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Object-oriented coder using block-based motion vectors and residual image compensation (블러기반 움직임 벡터와 오차 영상 보상을 이용한 물체지향 부호화기)

  • 조대성;박래홍
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.3
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    • pp.96-108
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    • 1996
  • In this paper, we propose an object-oriented coding method in low bit-rate channels using block-based motion vectors and residual image compensation. First, we use a 2-stage algorithm for estimating motion parameters. In the first stage, coarse motion parameters are estimated by fitting block-based motion vectors and in the second stage, the estimated motion parametes are refined by the gradient method using an image reconstructed by motion vectors detected in the first stage. Local error of a 6-parameter model is compensted by blockwise motion parameter correction using residual image. Finally, model failure (MF) region is reconstructed by a fractal mapping method. Computer simulation resutls show that the proposed method gives better performance than the conventional ones in terms of th epeak signal to noise ratio (PSNR) and compression ratio (CR).

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A 3-D Position Compensation Method of Industrial Robot Using Block Interpolation (블록 보간법을 이용한 산업용 로봇의 3차원 위치 보정기법)

  • Ryu, Hang-Ki;Woo, Kyung-Hang;Choi, Won-Ho;Lee, Jae-Kook
    • Journal of Institute of Control, Robotics and Systems
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    • v.13 no.3
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    • pp.235-241
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    • 2007
  • This paper proposes a self-calibration method of robots those are used in industrial assembly lines. The proposed method is a position compensation using laser sensor and vision camera. Because the laser sensor is cross type laser sensor which can scan a horizontal and vertical line, it is efficient way to detect a feature of vehicle and winding shape of vehicle's body. For position compensation of 3-Dimensional axis, we applied block interpolation method. For selecting feature point, pattern matching method is used and 3-D position is selected by Euclidean distance mapping between 462 feature values and evaluated feature point. In order to evaluate the proposed algorithm, experiments are performed in real industrial vehicle assembly line. In results, robot's working point can be displayed 3-D points. These points are used to diagnosis error of position and reselecting working point.

Reconstruction of Neural Circuits Using Serial Block-Face Scanning Electron Microscopy

  • Kim, Gyu Hyun;Lee, Sang-Hoon;Lee, Kea Joo
    • Applied Microscopy
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    • v.46 no.2
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    • pp.100-104
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    • 2016
  • Electron microscopy is currently the only available technique with a spatial resolution sufficient to identify fine neuronal processes and synaptic structures in densely packed neuropil. For large-scale volume reconstruction of neuronal connectivity, serial block-face scanning electron microscopy allows us to acquire thousands of serial images in an automated fashion and reconstruct neural circuits faster by reducing the alignment task. Here we introduce the whole reconstruction procedure of synaptic network in the rat hippocampal CA1 area and discuss technical issues to be resolved for improving image quality and segmentation. Compared to the serial section transmission electron microscopy, serial block-face scanning electron microscopy produced much reliable three-dimensional data sets and accelerated reconstruction by reducing the need of alignment and distortion adjustment. This approach will generate invaluable information on organizational features of our connectomes as well as diverse neurological disorders caused by synaptic impairments.

A Sharing Scheme for Connection Mamagement Objects in Different Distributed Processing Environments (이기종 분산처리환경상에서 연결관리 객체의 정보공유)

  • 신영석;오현주
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.4
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    • pp.793-803
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    • 1997
  • Open networking architecture is required to support new multimedia services as integrated functions of network management and service architecture. In this paper, we propose the methodology of building block modeling using object grouping concepts and the sharing scheme of different distributed processing environments based on open networking architecture. The building block has the functions of object management, security object instance registry and object mapping in object group. It is necessary for the connection management information to be shared on the interworking between two domains. We implemented and validated connection management functions using computational object modeling and building block modeling in different distributed processing environments.

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A Study on the Gray Scale Method of Digital LCOS Micro-display for Pico-projector Application (초소형 프로젝터를 위한 디지털 LCOS 마이크로 디스플레이의 계조 연구)

  • Kim, Min-Seok;Kang, Jung-Won
    • Journal of the Semiconductor & Display Technology
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    • v.9 no.2
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    • pp.87-90
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    • 2010
  • A new SRAM pixel circuit with RESET Transistor of a LCOS display module was designed for a pico-projector application. A dual-block PWM method was also proposed to realize the field sequential color system having only one LCOS panel. 0.29 inch LCOS panel in SVGA resolution was fabricated and the proposed dual-block PWM method was tested with it. Discontinuity of brightness curve was caused due to multi-pulses and it was improved by the adoption of proper mapping table. With the proposed SRAM with RESET pixel circuit and dual-block PWM method, the test images were successfully demonstrated.

Adaptive local histogram modification method for dynamic range compression of infrared images

  • Joung, Jihye
    • Journal of the Korea Society of Computer and Information
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    • v.24 no.6
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    • pp.73-80
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    • 2019
  • In this paper, we propose an effective dynamic range compression (DRC) method of infrared images. A histogram of infrared images has narrow dynamic range compared to visible images. Hence, it is important to apply the effective DRC algorithm for high performance of an infrared image analysis. The proposed algorithm for high dynamic range divides an infrared image into the overlapped blocks and calculates Shannon's entropy of overlapped blocks. After that, we classify each block according to the value of entropy and apply adaptive histogram modification method each overlapped block. We make an intensity mapping function through result of the adaptive histogram modification method which is using standard-deviation and maximum value of histogram of classified blocks. Lastly, in order to reduce block artifact, we apply hanning window to the overlapped blocks. In experimental result, the proposed method showed better performance of dynamic range compression compared to previous algorithms.

Preparation and characteristics of $HfO_2$ and $CeO_2$ doped 3Y-TZP block for dental ceramic block ($HfO_2$$CeO_2$가 첨가된 3Y-TZP 치과용 블록의 제조 및 특성 평가)

  • Ji, Sang-Yong;Ji, Hyung-Bin;Park, Hong-Chae;Yoon, Seog-Young
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.19 no.6
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    • pp.311-317
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    • 2009
  • 3Y-TZP block doped with $HfO_2$ and $CeO_2$ for dental ceramic block to the proliferation of CAD/CAM systems was prepared by heating at $800{\sim}1100^{\circ}C$ and then sintering at $1450^{\circ}C$. The influences of heating temperature and addition of $HfO_2$ and $CeO_2$ on the mechanical and chemical properties of 3Y-TZP block were investigated. Using the EDS mapping images, $HfO_2$ and $CeO_2$ was well dispersed in the 3Y-TZP matrix. 3 wt% $HfO_2$ doped block showed the optimum biaxial strength (1 GPa), while 3 wt% $CeO_2$ doped block enhanced the stability of $t-ZrO_2$ under hydrothermal atmosphere.

A Study on the Pattern Recognition based Distance Protective Relaying Scheme in Power System (전력계통의 패턴인식형 거리계전기법에 관한 연구)

  • 이복구;윤석무;박철원;신명철
    • Journal of the Korean Institute of Intelligent Systems
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    • v.8 no.2
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    • pp.9-20
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    • 1998
  • In this paper, a new distance relaying scheme is proposed. Artificial neural networks are applied to the distance relaying system composed of pattern recognition based. The proposed distance relaying scheme has two blocks of pattern recognition stages to estimate the fundamental frequency and to classify the fault types. In the first block, a filtering method using neural networks called a neural networks mapping filter(NMF) is presented to efficiently extract the features. And in the sec'ond block, the estimator called neural networks fault pattern estimator(NFPE) is also presented to classify the fault types by the extracted effective features obtained from NMF. Each block of these applied schemes is trained by back-propagation algorithm of multilayer perceptron and show the fast and accurate pattern recognition by ability of multilayer neural networks. The test result of this approach are obtained the good performance from the fault transient wave signals of EMTP(e1ectromagnetic transients program) in the various fault conditions of power systems.

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Implementation of Image Enhancement Filter System Using Genetic Algorithm (유전자 알고리즘을 이용한 영상개선 필터 시스템 구현)

  • Gu, Ji-Hun;Dong, Seong-Su;Lee, Jong-Ho
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.51 no.8
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    • pp.360-367
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    • 2002
  • In this paper, genetic algorithm based adaptive image enhancement filtering scheme is proposed and Implemented on FPGA board. Conventional filtering methods require a priori noise information for image enhancement. In general, if a priori information of noise is not available, heuristic intuition or time consuming recursive calculations are required for image enhancement. Contrary to the conventional filtering methods, the proposed filter system can find optimal combination of filters as well as their sequent order and parameter values adaptively to unknown noise types using structured genetic algorithms. The proposed image enhancement filter system is mainly composed of two blocks. The first block consists of genetic algorithm part and fitness evaluation part. And the second block consists of four types of filters. The first block (genetic algorithms and fitness evaluation blocks) is implemented on host computer using C code, and the second block is implemented on re-configurabe FPGA board. For gray scale control, smoothing and deblurring, four types of filters(median filter, histogram equalization filter, local enhancement filter, and 2D FIR filter) are implemented on FPGA. For evaluation, three types of noises are used and experimental results show that the Proposed scheme can generate optimal set of filters adaptively without a pioi noise information.

Development of CPLD technology mapping control algorithm for Sequential Circuit under Time Constraint (시간제약 조건하에서 순차 회로를 위한 CPLD 기술 매핑 제어 알고리즘 개발)

  • Youn, Chung-Mo;Kim, Jae-Jin
    • Journal of the Korean Institute of Telematics and Electronics T
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    • v.36T no.4
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    • pp.71-81
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    • 1999
  • We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.

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