• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.2
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• pp.87-95
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• 2002

In this paper, we proposed a fast multi-resolution motion estimation(MRME) algorithm. This algorithm exploits the half-pixel accuracy motion estimation(HPAME) for exact motion vectors in the baseband and block classification for the reduction of bit amounts and computational loads. Generally, as the motion vector in the baseband are used as initial motion vector in the high frequency subbands, it has crucial effect on quality of the motion compensated image. For this reason, we exploit HPAME in the motion estimation for the baseband. But HPAME requires additional bit and computational loads so that we use block classification for the selective motion estimation in the high frequency subbands to compensate these problems. In result, we could reduce the bit rate and computational load at the similar image quality with conventional MRME. The superiority of the proposed algorithm was confirmed by the computer simulation.

• Journal of the Korea Convergence Society
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• v.11 no.12
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• pp.15-22
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• 2020

In this paper, we proposed a deep learning based super-resolution method that combines Channel Attention and Spatial Attention feature enhancement methods. It is important to restore high-frequency components, such as texture and features, that have large changes in surrounding pixels during super-resolution processing. We proposed a super-resolution method using feature enhancement that combines Channel Attention and Spatial Attention. The existing CNN (Convolutional Neural Network) based super-resolution method has difficulty in deep network learning and lacks emphasis on high frequency components, resulting in blurry contours and distortion. In order to solve the problem, we used an emphasis block that combines Channel Attention and Spatial Attention to which Skip Connection was applied, and a Residual Block. The emphasized feature map extracted by the method was extended through Sub-pixel Convolution to obtain the super resolution. As a result, about PSNR improved by 5%, SSIM improved by 3% compared with the conventional SRCNN, and by comparison with VDSR, about PSNR improved by 2% and SSIM improved by 1%.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.1
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• pp.55-63
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• 2000

This paper investigated the sub-region compression effect of the three dimensional DCT(3D-DCT) using the difference component(DC) of inter-frame in images. The proposed algorithm are the method that obtain compression effect to divide the information into subband after 3D-DCT, the data appear the type of cubic block(8${\times}$8${\times}$8) in eight difference components per unit. In the frequence domain that transform the eight differential component frames into eight DCT frames with components of both spatial and temporal frequencies of inter-frame, the image data are divided into frame component(8${\times}$8 block) of time-axis direction into 4${\times}$4 sub block in order to effectively obtain compression data because image components are concentrate in corner region with low-frequency of cubic block. Here, using the weight of sub block, we progressed compression ratio as consider to adaptive sub-region of low frequency part. In simulation, we estimated compression ratio, reconstructed image resolution(PSNR) with the simpler image and the complex image contained the higher frequency component. In the result, we could obtain the high compression effect of 30.36dB(average value in the complex-image) and 34.75dB(average value in the simple-image) in compression range of 0.04~0.05bpp.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.61-69
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• 2010

In this paper, an 1.2V 8b 800MSPS A/D Converter(ADC) with an odd number of folding block to overcome the asymmetrical boundary-condition error is described. The architecture of the proposed ADC is based on a cascaded folding architecture using resistive interpolation technique for low power consumption and high input frequency. The ADC employs a novel odd folding block to improve the distortion of signal linearity and to reduce the offset errors. In the digital block, furthermore, we use a ROM encoder to convert a none-$2^n$-period code into the binary code. The chip has been fabricated with an $0.13{\mu}m$ 1P6M CMOS technology. The effective chip area is $870{\mu}m\times980{\mu}m$. SNDR is 44.84dB (ENOB 7.15bit) and SFDR is 52.17dBc, when the input frequency is 10MHz at sampling frequency of 800MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Journal of Nutrition and Health
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• v.51 no.6
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• pp.590-598
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• 2018

Purpose: This study was conducted to compare the food involvement scale (FIS) of American and Japanese consumers. In addition, the effects of familiarity, likability, and expectations on willingness to use intentions for block type sauce by nationality were evaluated. Methods: A total of 149 and 112 American and Japanese consumers, respectively, completed the survey. Consumers were asked about familiarity, likability, expectation, willing to use intention, and usage frequency of block type sauce, food involvement scale (FIS), and demographic information. Results: There were differences in the using frequency of block type sauce according to nationality, with consumers in Japan showing significantly higher frequency of using block type sauce than those in the United States (US) (p < 0.001). According to the FIS, US consumers were more focused on how to provide food than food, such as cooking process, table setting, and food shopping, compared to Japanese consumers. In addition, 'expectation' and 'likability' among US consumers and 'expectation' and 'familiarity' among Japanese consumers were positive attributes for willing to use intention (p < 0.01). Conclusion: In the case of the US consumers, 'familiarity' was not significant because the using frequency of the block type sauce was lower than that of Japanese consumers. In the case of the Japanese consumers, 'likability' was not significant because they enjoy cooking itself according to the FIS. Therefore, it is necessary to recognize positive attributes as a key factor for block type sauce, as well as to search for ways to apply marketing strategies based on attributes by nationality.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.2 no.2
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• pp.3-10
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• 1991

The new structure method of GaAs microwave amplifiers using DC block function and impedance transforming property of DC block/transformer(non-symmetrical two - microstrip coupled line and interdigital three - microstrip coupled line), instead of chip capacitor, is presented. The newly structured microwave amplifier showed wideband characteristics(bandwidth, 3.5 GHz) and flat frequency response. Interdigital three - microstrip coupled line which is used for microwave amplifier can be used to match amplifiers as well as DC blocking.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1589-1598
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• 1999

Conventional MSE or PSNR based methods for objective picture quality assessment of moving picture coder are not well correlated with subjective human evaluation. In recent years, the design of better objective quality assessment has attracted much intention and several picture quality metrics based on the properties of Human Visual System has been proposed. This paper proposes new metric which is appropriate for objective picture quality assessment of block based moving picture coder by considering frequency sensitivity, inter-intra channel masking and several distortion artifacts caused by block based coding. The experimental results show that the proposed method is good correlated with subjective assessment.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.131-136
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MB-OFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MB-OFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.91-95
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• 2008

This paper presents a direct-conversion I/Q up-mixer block, which supports $3{\sim}5$ GHz ultra-wideband(UWB) applications. It consists of a VI converter, a double-balanced mixer, a RF amplifier, and a differential-to-single signal converter. To achieve wideband characteristics over $3{\sim}5$ GHz frequency range, the double-balanced mixer adopts a shunt-peaking load. The proposed RF amplifier can suppress unwanted common-mode input signals with high linearity. The proposed direct-conversion I/Q up-mixer block is implemented using $0.18-{\mu}m$ CMOS technology. The measured results for three channels show a power gain of $-2{\sim}-9$ dB with a gain flatness of 1dB, a maximum output power level of $-7{\sim}-14.5$ dBm, and a output return loss of more than - 8.8 dB. The current consumption of the fabricated chip is 25.2 mA from a 1.8 V power supply.