• 한국CDE학회논문집
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• 제17권6호
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• pp.409-416
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• 2012

Most of the shipbuilding scheduling researches so far have been conducted with stress on the dock plan. That is due to the fact that the dock is the least extendable resource in shipyards and its overloading is difficult to resolve. However, once the dock scheduling is completed, it is also important to make a plan that make the best use of the rest of the resources in the shipyard, so that any additional cost is minimized. This study automates block allocation process by analyzing the existing manual process that designates production bays for the blocks during the midterm planning. Also, a planning scenario validation method is suggested, where block allocation scenarios based on diagrams are edited and simulated.

• 산업공학
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• 제20권3호
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• pp.395-406
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• 2007

In the telecommunication industry, estimation of the cost of network facilities is very important since depreciation cost of the facilities accounts for a large portion of the product cost. Moreover, cost estimation in the industry becomes more difficult because of increasing indirect cost upon digital convergence, expanding multi-purpose facilities, complexity of service product, etc. Nevertheless, not much seem to have been done in improving estimation methodology of the cost of network facilities. As a result, the quality of cost information on network facilities has deteriorated, and now even decision-makers in the industry dismiss the information. Recently, two major telecommunication companies adopted a new network cost estimation method to deal with the issue. In this paper, we study the concept of new cost estimation method and the procedure to develop and apply it. We also suggest the method to carry out the cost allocation using Matlab which is more efficient and time-saving than other commercial cost calculation packages.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.309-317
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• 2011

This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 ${\mu}m$ CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/${\surd}$Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.

• International Journal of Naval Architecture and Ocean Engineering
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• 제6권1호
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• pp.162-174
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• 2014

Most shipbuilding scheduling research so far has focused on the load level on the dock plan. This is because the dock is the least extendable resource in shipyards, and its overloading is difficult to resolve. However, once dock scheduling is completed, making a plan that makes the best use of the rest of the resources in the shipyard to minimize any additional cost is also important. Block assignment planning is one of the midterm planning tasks; it assigns a block to the facility (factory/shop or surface plate) that will actually manufacture the block according to the block characteristics and current situation of the facility. It is one of the most heavily loaded midterm planning tasks and is carried out manually by experienced workers. In this study, a method of representing the block assignment rules using a diagram was suggested through analysis of the existing manual process. A block allocation program was developed which automated the block assignment process according to the rules represented by the diagram. The planning scenario was validated through a case study that compared the manual assignment and two automated block assignment results.

• 한국정보과학회논문지:시스템및이론
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• 제32권5호
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• pp.232-242
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• 2005

이 논문에서는 빠른 하드웨어/소프트웨어 통합합성을 위해 데이타플로우 그래프(DFG: Dataflow Graph)로부터 하드웨어를 자동으로 합성하는 내용을 다룬다. 이 데이타플로우 그래프에서 로드는 FIR(Finite Impulse Response) 필터나 DCT(Discrete Cosine Transform) 블록과 같이 크기가 어느 정도 되는 하드웨어 블록을 나타내며, 이 노드의 포트는 한번 수행할 때마다 하나 이상의 데이타 샘플을 주고 받을 수 있다. 즉, 멀티레이트 데이타 샘플(multi-rate data sample)을 교환한다. 이러한 특성들은 기존의 Behavioral Synthesis와 구별되는 점이며, 따라서 Behavioral Synthesis보다 어려운 문제가 된다. 본 논문에서 제안하는 설계 방법을 사용하면 알고리즘을 명세하는 데이타플로우 그래프는 하드웨어 리소스의 할당과 스케줄 정보에 따라 다양한 하드웨어 구조로 매핑될 수 있다. 따라서 하드웨어 설계시에 면적/성능 트레이드오프 관계를 손쉽게 관리할 수 있으며, 하드웨어를 자동으로 합성하는 기존의 방식보다구현 가능한 하드웨어 설계 공간을 더욱 넓혀주는 효과를 거둘 수 있다.