• Journal of Korean Institute of Industrial Engineers
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• v.33 no.1
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• pp.110-125
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• 2007

Various different types of yard cranes are used in container terminals. Examples are rubber tired gantry cranes,rail mounted gantry cranes, overhead bridge cranes, dual rail-mounted gantry cranes, and automated stacking cranes. The kinematics and handling characteristics of these yard cranes are different from each other. Ttiis study analyses charactehstics of generic types of yard cranes which represent various yard cranes m practice Demg used in several types of block layouts, Considering specifications of yard cranes and block layouts, expected cycle times and variances of the cycle time are estimated for different handling activities.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.17 no.30
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• pp.1-9
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• 1994

In this study the recent papers and articles related to facility layout are reviewed to identify the factors to be considered on the development of block layouts. The factors found on the articles are used in the questionnaire to find out the desired closeness ratings for them in machinery plants. The weights found at the survey are used on the development of layouts using CORELAP with examples as a demonstration purpose.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• Journal of Korean Institute of Industrial Engineers
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• v.27 no.1
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• pp.54-60
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• 2001

In this paper, a shape-based block layout (SBL) approach is presented to solve the facility layout problem with unequal-area and fixed shapes. The SBL approach employs hybrid genetic algorithm (Hybrid-GA) to find a good solution and the concept of bay structure is used. In the typical facility layout problem with unequal area and fixed shapes, the given geometric constraints of unequal-area and fixed shapes are mostly approximated to original shape by aspect ratio. Thus, the layout results require extensive manual revision to create practical layouts and it produces irregular building shapes and too much unusable spaces. Experimental results show that a SBL model is able to produce better solution and to create more practical layouts than those of existing approaches.

• IE interfaces
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• v.19 no.2
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• pp.160-167
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• 2006

It is a crucial managerial issue how to manage assembly blocks at shipyard. Based on the project experience in Hyundai Heavy Industries, this study points out the difficulties on the block stockyard operations, formalizes the JIBUN (location) assignment problem for assembly blocks, and develops the JIBUN (location) assignment algorithm whose purpose is to reduce the number of unproductive block moves. Through simulation experiments for various situations, this study demonstrates the usefulness of JIBUN (location) assignment algorithm. In addition, this study examines the impacts of block move sequence rules and of block stockyard layouts on the block stockyard operations.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.246-249
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• 2000

In this paper, we describe an automated extraction program that transforms a mask layout into an approximated equivalent circuit information suitable for circuit simulation, and that extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. To extract equivalent circuit from mask layout, we propose new block disassembly technique capable of accurate computations of distributed RCs at branch point, using vectorized edges which represent the outline of an individual polygon.

• IE interfaces
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• v.22 no.2
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• pp.116-125
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• 2009

We revisit the assembly block storage location assignment problem (ABSLAP) at a shipyard, in order to compensate for the deficiency in performance verification of the heuristic ABSLAP algorithm developed by the previous study. In this paper, we formulate a mathematical programming model of the ABSLAP, refine elaborately the heuristic ABSLAP algorithm, and show the performance of the developed mathematical programming model and the revised heuristic ABSLAP algorithm. In addition, we explain simulation experiments conducted using the revised heuristic ABSLAP algorithm to investigate the influences of block stockyard layouts and production schedule instability on the block stockyard operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.75-84
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• 2001

Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1989.10a
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• pp.77-85
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• 1989

The purpose of this research entails the study of the multicriteria graph-theoretic Facility Layout Problem(FLP), the development of a Decision Support System(DSS), and a sensitivity analysis for graph Theoretic heuristics. The graph theoretic FLP Decision Support System gives decision makers or planners more information as a guide in producing their final layouts. This information is provided by a variety of final result scores, so called upper bound values, based on different options and different criteria. The increased information provided will give decision makers more confidence in design a block plan. One case is presented to demonstrate the applicability of the system to real-world problem. Finally, applicabilities of the DSS to other format layouts, such as GT layout and JIT's U-line, are briefly mentioned.

• The Korean Journal of Applied Statistics
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• v.4 no.1
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• pp.25-32
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• 1991

An Asymptotically distribution-free test is considered for testing parallelism against ordered alternatives in two-way layouts. The test procedure is based on a statistic which uses Jonckheere's idea after adjusting the block effects. Large-sample properties including the efficiency and limiting distribution of the test statistic are obtained. The proposed test is compared with other tests through a small-sample Monte Carlo study.