• Proceedings of the KIEE Conference
• /
• 1998.07g
• /
• pp.2470-2472
• /
• 1998

In this paper, we proposed the method to improve the performance of Viterbi decoder by applying Concatenated structure. Proposed decoder for Concatenated Code is designed with inner Viterbi decoder, block deinterleaver and outer Viterbi decoder. Inner Viterbi decoder (K=7, R=1/2) has 8-level soft decision, but outer decoder (K=7, R= 1/2) has 2-level hard decision. Applied interleaving scheme make decoder to have better BER performance in Concatenated code. The designed VLSI shares inner decoder with outer decoder. Because of sharing structure, complexity of decoder can be reduced to half. But it required about twice clock speed.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.17 no.8
• /
• pp.2068-2082
• /
• 2023

With the rapid development of deep learning, Depth Map Super-Resolution (DMSR) method has achieved more advanced performances. However, when the upsampling rate is very large, it is difficult to capture the structural consistency between color features and depth features by these DMSR methods. Therefore, we propose a color-image guided DMSR method based on iterative depth feature enhancement. Considering the feature difference between high-quality color features and low-quality depth features, we propose to decompose the depth features into High-Frequency (HF) and Low-Frequency (LF) components. Due to structural homogeneity of depth HF components and HF color features, only HF color features are used to enhance the depth HF features without using the LF color features. Before the HF and LF depth feature decomposition, the LF component of the previous depth decomposition and the updated HF component are combined together. After decomposing and reorganizing recursively-updated features, we combine all the depth LF features with the final updated depth HF features to obtain the enhanced-depth features. Next, the enhanced-depth features are input into the multistage depth map fusion reconstruction block, in which the cross enhancement module is introduced into the reconstruction block to fully mine the spatial correlation of depth map by interleaving various features between different convolution groups. Experimental results can show that the two objective assessments of root mean square error and mean absolute deviation of the proposed method are superior to those of many latest DMSR methods.

• ETRI Journal
• /
• v.27 no.5
• /
• pp.525-532
• /
• 2005

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.11B
• /
• pp.1556-1564
• /
• 2001

Reed-Solomon code, block interleaving and SI (side information) are frequently used in SFH (slow frequency hopping) system. Erasing those symbols in the hit frequency slot greatly increases the error connection capacity. Packet error rate has been the major performance measure for SFH system. The analysis of BER has been limited to the case of perfect Sl, in which neither miss nor false alarm exists. BER with imperfect Sl has been obtained only by Monte Carlo simulation. In this paper, we present a unified solution to estimate BER with imperfect Sl. It is shown that previous formulae for packet error rate or BER with perfect Sl are special cases in the proposed solution. The computed BER with false alarm and miss of frequency hit is verified by comparing with the simulation result.

• Journal of electromagnetic engineering and science
• /
• v.6 no.3
• /
• pp.147-154
• /
• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.6 no.4
• /
• pp.3-38
• /
• 1996

The mobile station shall convolutionally encode the data transmitted on the reverse traffic channel and the access channel prior to interleaving. Code symbols output from the convolutional encoder are repeated before being interleaved except the 9600 bps data rate. All the symbols are then interleaved, 64-ary orthogonal modulation, direct-sequence spreading, quadrature spreading, baseband filtering and QPSK transmission. The sync, paging, and forward traffic channel except the pilot channel in the forward CDMA channel are convolutionally encoded, block interleaved, spread with Walsh function at a fixed chip rate of 1.2288 Mcps to provide orthogonal channelization among all code channels. Following the spreading operation, the I and Q impulses are applied to respective baseband filters. After that, these impulses shall be transmitted by QPSK. Authentication in the CDMA system is the process for confirming the identity of the mobile station by exchanging information between a mobile station and the base station. The authentication scheme is to generate a 18-bit hash code from the 152-bit message length appended with 24-bit or 40-bit padding. Several techniques are proposed for the authentication data computation in this paper. To protect sensitive subscriber information, it shall be required enciphering ceratin fields of selected traffic channel signaling messages. The message encryption can be accomplished in two ways, i.e., external encryption and internal encryption.

• Journal of IKEEE
• /
• v.26 no.3
• /
• pp.506-509
• /
• 2022

In a secret sharing scheme, secret information must be distributed and stored to users, and confidentiality must be able to be reconstructed only from an authorized subset of users. To do this, secret information among different code words must not be subordinate to each other. The minimal code is a kind of linear block code to distribute these secret information not mutually dependent. In this paper, we present a novel extension technique for minimal codes. The product of an arbitrary vector and a minimal code produces a new minimal code with an extended length and Hamming weight. Accordingly, it is possible to provide minimal codes with parameters not known in the literature.

• Journal of Computing Science and Engineering
• /
• v.5 no.2
• /
• pp.111-120
• /
• 2011

Data mining algorithms should exploit new hardware technologies to accelerate computations. Such goal is difficult to achieve in database management system (DBMS) due to its complex internal subsystems and because data mining numeric computations of large data sets are difficult to optimize. This paper explores taking advantage of existing multithreaded capabilities of multicore CPUs as well as caching in RAM memory to efficiently compute summaries of a large data set, a fundamental data mining problem. We introduce parallel algorithms working on multiple threads, which overcome the row aggregation processing bottleneck of accessing secondary storage, while maintaining linear time complexity with respect to data set size. Our proposal is based on a combination of table scans and parallel multithreaded processing among multiple cores in the CPU. We introduce several database-style and hardware-level optimizations: caching row blocks of the input table, managing available RAM memory, interleaving I/O and CPU processing, as well as tuning the number of working threads. We experimentally benchmark our algorithms with large data sets on a DBMS running on a computer with a multicore CPU. We show that our algorithms outperform existing DBMS mechanisms in computing aggregations of multidimensional data summaries, especially as dimensionality grows. Furthermore, we show that local memory allocation (RAM block size) does not have a significant impact when the thread management algorithm distributes the workload among a fixed number of threads. Our proposal is unique in the sense that we do not modify or require access to the DBMS source code, but instead, we extend the DBMS with analytic functionality by developing User-Defined Functions.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.10A
• /
• pp.1571-1578
• /
• 1999

In this paper, we present the Modulator Channel Card and VLSI chip for the Radio Transceiver Unit (RTU) of direct sequence code division multiple access (DS-CDMA) Wireless Local Loop (WLL) System. The Modulator Channel Card is designed and implemented using ASIC's, FPGA's and DSP's. The ASIC, compliance with Common Air Interface specification proposed by ETRI, has 40K gates which is designed to operate at 32MHz, and is fabricated using $0.6\mu\textrm{m}$ CMOS process. The ASIC carries out for I- or Q- phase data channel signal processing at a time, where each data channel processing consists of channel coding, block interleaving, scrambling, Walsh modulation, Pseudo-Noise (PN) spreading, and baseband filtering. The Modulator Channel Card has been integrated as a part of RTU of WLL system and is confirmed that it meets all functional and performance requirements.

• KIPS Transactions on Computer and Communication Systems
• /
• v.2 no.9
• /
• pp.381-392
• /
• 2013

During the last decade, the multitude of advances attained in terminal computers, along with the introduction of mobile hand-held devices, and the deployment of high speed networks have led to a recent surge of interest in Quality of Service (QoS) for video applications. The main difficulty is that mobile devices experience disparate channel conditions, which results in different rates and patterns of packet loss. One way of making more efficient use of network resources in video services over wireless channels with heterogeneous characteristics to heterogeneous types of mobile device is to use a scalable video coding (SVC). An SVC divides a video stream into a base layer and a single or multiple enhancement layers. We have to ensure that the base layer of the video stream is successfully received and decoded by the subscribers, because it provides the basis for the subsequent decoding of the enhancement layer(s). At the same time, a system should be designed so that the enhancement layer(s) can be successfully decoded by as many users as possible, so that the average QoS is as high as possible. To accommodate these characteristics, we propose an efficient transmission scheme which incorporates SVC-aware dual-channel repetition to improve the perceived quality of services. We repeat the base-layer data over two channels, with different characteristics, to exploit transmission diversity. On the other hand, those channels are utilized to increase the data rate of enhancement layer data. This arrangement reduces service disruption under poor channel conditions by protecting the data that is more important to video decoding. Simulations show that our scheme safeguards the important packets and improves perceived video quality at a mobile device.