• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.1 s.307
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• pp.91-100
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• 2006

A scheme is proposed for implementing the block LMS algorithm in a block floating point framework that permits processing of data over a wide dynamic range at a processor complexity and coat as low as that of a fixed point processor. The proposed scheme adopts appropriate formats for representing the filter coefficients and the data. Using these and a new upper bound on the step size, update relations for the filter weight mantissas and exponent are developed, taking care so that neither overflow occurs, nor are quantifies which are already very small multiplied directly. It is further shown how the mantissas of the filter coefficients and also the filter output can be evaluated faster by suitably modifying the approach of the fast block LMS algorithm

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.963-972
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• 2002

An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-$\mu\textrm{m}$ CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. It was verified by Xilinx FPGA implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.65-73
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• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.95-117
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• 2006

In this paper, we describe the optimization of the link-level performance and the complexity of floating-point and fixed-point methods in IEEE 802.16e OFDMA/TDD mobile modem. In floating-point design, we propose the channel estimation methods for downlink traffic channel and select the optimized method using computer simulation. So we also propose efficent algorithms for time and frequency synchronization, Digital Front End and CINR estimation scheme to optimize the system performance. Furthermore, we describe fixed-point method of uplink traffic and control channels. The superiority of the proposed algorithm is validated using the performances of Detection, False Alarm, Missing Probability and Mean Acquisition Time, PER Curve, etc. For fixed-point design, we propose an efficient methodology for optimized fixed-point design from floating-point At last, we design fixed-point of traffic channel, time and frequency synchronization, DFE block in uplink and downlink. The tradeoff between performance and complexity are optimized through computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.365-374
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• 1996

Finite wordlength effects of the FS-1016 CELP(Code Excite Linear Prediction) vocoder algorithm) is analyzed, and a block floating-Point implementation method is employed to improve the fixed-point performance. An efficient run-time integer wordlength estimation algorithm is developed, and the overall system performance. An efficient run-time integer wordlength estimation algorithm is developed, and the overall system performance is verified in real-time using a TMS320C50 emulation board. Autoscaler software that conducts simulation-based automatic scaling to provide a floating-point like programming environment is used for this application development.

• The Transactions of the Korea Information Processing Society
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• v.6 no.11
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• pp.3140-3149
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• 1999

Skew correction for document images can be using a rotational transformation of pixel coordinates. In this paper we propose a method which corrects the document skew, by an amount of $\theta$ degrees, using block information, where the block is defined as a rectangular area containing adjacent black pixels. Processing speed of the proposed method is faster than that of the method using pixel transformation, since the number of floating-point operations can be reduced significantly. In the proposed method, we rotate only the four corner points of each block, and then identify the pixels inside the block. Two methods for inside pixel identification are proposed; the first method finds two points intersecting the boundary of the rotated block in each row, and determines the pixels between the two intersection points as the inside pixel. The second method finds boundary points based on Bresenham's line drawing algorithm, using fixed-point operation, and fills the region surrounded by these boundaries as black pixels. We have measured the performance of the proposed method by experimenting it with 2,016 images of various English and Korean documents. We have also proven the superiority of our algorithm through performance comparison with respect to existing methods based on pixel transformation.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.165-168
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• 2001

This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.

• Journal of the Korean Institute of Navigation
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• v.10 no.2
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• pp.83-96
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• 1986

In the restricted sea way such as fair way in harbor, narrow channel etc, the safe ship-handling is a very important problem, which is greatly related with turning ability of ships. It is of great importance that ship-handlers can grasp the position of pivoting point varying with time increase at any moment for relevant steering activities. Mean while, in advanced ship-building countries they study and investigated pivoting point related with turning characteristics, hut their main interest lies in ship design, not in safe ship controlling and maneuvering. In this regards it is the purpose of this paper to provide ship-handlers better under standing of pivoting point location together with turning characteristics and then to help them in safe ship-handling by presenting fact that pivoting points vary according to configuration of ships. The author calculated the variation of pivoting point as per time increase for various type of vessels, based on the hydrodynamic derivatives obtained at test of Davidson Laboratory of Stevens Institutes of Technology , New Jersey, U.S.A. The results were classified and investigated according to the magnitude of block coefficient , length-beam ratio, length-draft ratio, rudder area ratio ete, and undermentioned results were obtained. (1) The trajectory of pivoting point due to variation of rudder angle are all the same at any time, though the magenitude of turning circle are changed variously. (2) The moving of pivoting point is affected by the magnitude of block coefficient, length-beam ratio, length-draft ratio, however the effect by rudder area ratio might be disregarded. (3) In controlling and maneuvering of vessels in harbor, ship-handlers might regard that the pivoting point would be placed on 0.2~0.3L forward from center of gravity at initial stage. (4) The pivoting point of VLCC or container feeder vessels which have block coefficient more than 0.8 and length-beam ratio less than 6.5 are located on or over bow in the steady turning. (5) When a vessel intends to avoid some floating obstruction such as buoy forward around her eourse, the ship-handler might consider that the pivoting point would be close by bow in ballast condition and cloase by center of gravity in full-loaded condition.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1215-1218
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• 1998

본 논문은 Digital Audio Compression(AC-3) Standard 인 A-52를 기반으로 하였으며 Borland C++3.1 Compiler를 사용하여 AC-3 Decoding Algorithm 구현하였다. Input Stream은 DVD VOB File에서 AC-3 Stream만을 분리하여 사용하며 최종 출력은 16 Bit PCM File이다. AC-3의 Frame구조는 Synchronization Information, Bit Stream Information, Audio Block, Auxiliary Data, Error Check로 구성된다. Aduio Block 은 모두 6개의 Block으로 나뉘어져 있다. BSI와 Side Information을 참조하여 Exponent를 추출하여 Exponent Strategy에 따라 Exponent를 복원한다. 복원된 Exponent 정보를 이용하여 Bit Allocation을 수행하여 각각의 Mantissa에 할당된 Bit수를 계산하고 Stream으로부터 Mantissa를 추출한다. Coupling Parameter를 참조하ㅕ Coupling Channel을 Original Channel로 복원시킨다. Stereo Mode에 대해서는 Rematrixing을 수행한다. Dynamic Range는 Mantissa와 Exponent의 Magnitude를 바꾸는 것으로 선택적으로 사용할 수 있다. Mantissa와 Exponent를 결합하여 Floating Point coefficient로 만든 후 Inverse Transform을 수행하면 PCM Data를 얻을 수 있다. PC에서 듣기 위해서는 Multi Channel을 Stereo나 Mono로 Downmix를 수행한다. 이렇게 만들어진 PCM data는 PCM Data를 재생하는 프로그램으로 재생할 수 있다.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.113-116
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• 2002

This paper describes a design of 8192-Point pipelined FFT/IFFT processor (PFFTSk) core for DVB-T and DMT-based VBSL modems. A novel two-step convergent block floating -point (75_CBFP) scaling method is proposed to improve the signal- to-quantization-noise ratio (SeNR) of FFT/IFFT results. Our approach reduces about 80% of memory when compared with conventional CBFP methods. The PFFTSk core, which is designed in VHDL and synthesized using 0.25-${\mu}{\textrm}{m}$ CMOS library, has about 76,300 gates, 390k bits RAM, and Twiddle factor ROM of 39k bits. Simulation results show that it can safely operate up to 50-MHz clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-$mutextrm{s}$. The SQNR of about 60-dB is achieved.