• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.332-336
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• 1991

Network management is responsible for gathering information on the usage of the network media by the network devices, ensuring the correct operation of the network, and providing reports. MAP network management must provide the high reliability of the media and signaling method, even in very harsh environments, providing a very low bit error rate and minimum number of retransmission. In this paper, we analysed the framework of OSI management and MAP network management and discussed the implementation method of fault management and remote management mechanism in the Mini-MAP controller developed for IBM-PC.

• Journal of KIISE
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• v.43 no.2
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• pp.186-195
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• 2016

This paper proposes a vehicle license plate detection method in real road environments using 8 bit-MCT features and a landmark-based Adaboost method. The proposed method allows identification of the potential license plate region, and generates a saliency map that presents the license plate's location probability based on the Adaboost classification score. The candidate regions whose scores are higher than the given threshold are chosen from the saliency map. Each candidate region is adjusted by the local image variance and verified by the SVM and the histograms of the 8bit-MCT features. The proposed method achieves a detection accuracy of 85% from various road images in Korea and Europe.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.725-732
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• 2002

Block-wise MAP (Maximum A posteriori) decoding algorithm for turbo-codes requires less memory than Log-MAP decoding algorithm. The ER (Bit Error Rate) performance of previous block-wise MAP decoding algorithm depend on the block length and training length. To maximize hardware utilization and perform successive decoding, the block length is set to be equal to the training length in previous MAP decoding algorithms. Simulation result on the BER performance shows that the EBR performance can be maintained with shorter blocks when training length is sufficient. This paper proposes an architecture for area efficient block-wise MAP decoder. The proposed architecture employs the decoding schema for reducing memory by using the training length, which in N times larger than block length. To efficiently handle the proposed schema, a pipelined architecture is proposed. Simulation results show that memory usage can be reduced by 30%~45% in the proposed architecture without degrading the BER performance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.2
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• pp.36-43
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• 1985

This paper describes a DRC (Design Rule Check) algorithm and its program implement-ation which requires CPU time linearly proportional to the number of rectangular patterns n the NMOS If layout. While the CPU time for conventional DRC algorithm is proportion-al to 0(nlogn) or 0(n**1.2), (n:number of rectangles it was shown that the present also-rithm only consumes CPU time linearly proportional to 0(n).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3B
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• pp.464-471
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• 2000

The number of quantization bits of the input signals $X_k$,$Y_k$ need to be optimally determined through the trade-off between the H/W complexity and the BER performance in Turbo codes applications. Also, an effective means to incorporate a channel reliability $L_c$ in the Log-MAP-based Turbo decoding is highly required. because it has a major effect on both the complexity and the performance. In this paper, a novel bit-shifting approach that substitutes for the multiplying is proposed so as to effectively incorporate. $L_c$ in Turbo decoding. The optimal number of quantization bits of $X_k$,$Y_k$ is investigated through Monte-Carlo simulations assuming that bit-shifting approach is adopted. In addition. The effects of an incorrect estimation of noise variance on the performance of Turbo codes is investigated. There is a confined range in which the effects of an incorrect estimation can be ignored.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.8
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• pp.629-637
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• 2013

Chaos communication systems have the characteristics such as non-periodic, wide-band, non-predictability of signals and easy implementation. There have been many studies about chaos communication systems because of these advantages. But, chaos communication systems have low BER(Bit Error Rate) compare to general digital communication system. Existing researches on chaos communication systems only analyze BER performance according to various chaos maps. There are no studies on analysis of BER performance according to PDF(Probability Density Function) of chaos maps. In this paper, we analyze the BER performance according to changing parameter, equation, and initial values of chaos map's PDF. In addition, we propose new chaos map to improve BER performance. Simulation results show that BER performance of CDSK(Correlation Delay Shift Keying) is changed when PDF of chaos map changed. And the proposed chaos map has a better BER performance compare to previous chaos maps such as Tent map, Logistic map, and Henon map.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.36-41
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• 2006

In this paper, we present the performance of iterative decoding with a Turbo decoder and a M-ary QAM(Quadrature Amplitude Modulation) demapper. The demappers are designed with Max-Log-MAP algorithm and it's approximated one. In addition, we provide implementing block for the approximated algorithm. From the results of computer simulations, the approximated algorithm of the Max-Log-MAP has little bit worse than the Max-Log-MAP but suggests low complexity for practical implementation.

• Journal of Korea Multimedia Society
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• v.14 no.2
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• pp.210-218
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• 2011

Generally, GIS digital map has been represented and transmitted by ASCII and Binary data forms. Among these forms, Binary form has been widely used in many GIS application fields for the transmission of mass map data. In this paper, we present a hierarchical compression technique of polyline and polygon components for effective storage and transmission of vector map with various degree of decision. These components are core geometric components that represent main layers in vector map. The proposed technique performs firstly the energy compaction of all polyline and polygon components in spatial domain for the lossless compression of detailed vector map and compress independently integer parts and fraction parts of 64bit floating points. From experimental results, we confirmed that the proposed technique has superior compressive performance to the conventional data compression of 7z, zip, rar and gz.

• Journal of KIISE:Information Networking
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• v.28 no.2
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• pp.262-276
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• 2001

Recently much research for developing forwarding table that support fast router without employing both special hardware and new protocols. This article introduces a new forwarding data structure based on the software to enable forwarding lookup to be penormed at giga-bit speed. The forwarding table is known as a bottleneck of the routers penormance due to its high complexity proportional to the forwarding table size. The recent research that based on the software uses a Patricia trie and its variants. and also uses a hash function with prefix length key and others. The proposed forwarding table structure construct a forwarding table by the bit stream array in which it constructs trie from routing table prefix entries and it represents each pointer pointing the child node and the associated forwarding table entry with one bit The trie structure and routing prefix pointer need a large memory when representing those by linked-list or array. but in the proposed data structure, the needed memory size is small enough since it represents information with one bit. Additionally, by use a lookup method that start searching at desired middle level we can shorten the search path. The introduced data structure. called bit-map trie shows that we can implement a fast forwarding engine on the conventional Pentium processor by reducing the backbone routing table fits into Level 2 cache of Pentium II processor and shortens the searching path. Our experiments to evaluate the performance of proposed method show that this bit-map trie accomplishes 5.7 million lookups per second.

• Journal of Sensor Science and Technology
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• v.7 no.2
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• pp.124-130
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• 1998

High-speed 3D vision systems are essential for autonomous robot or vehicle control applications. In our study, a stereo vision process has been developed. It consists of three steps : extraction of edges in right and left images, matching corresponding edges and calculation of the 3D map. This process is implemented in a VME 150/40 Imaging Technology vision system. It is a modular system composed by a display, an acquisition, a four Mbytes image frame memory, and three computational cards. Programmable accelerator computational modules are running at 40 MHz and are based on TMS320C31 DSP with a $64{\times}32$ bit instruction cache and two $1024{\times}32$ bit internal RAMs. Each is equipped with 512 Kbytes static RAM, 4 Mbytes image memory, 1 Mbytes flash EEPROM and a serial port. Data transfers and communications between modules are provided by three 8 bit global video bus, and three local configurable pipeline 8 bit video bus. The VME bus is dedicated to system management. Tasks between DSPs are distributed as follows: two DSPs are used to edges detection, one for the right image and the other for the left one. The last processor computes the matching process and the 3D calculation. With $512{\times}512$ pixels images, this sensor generates dense 3D maps at a rate of about 1 Hz depending of the scene complexity. Results can surely be improved by using a special suited multiprocessors cards.