• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.906-913
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• 2009

In this paper, the design concept and implementation method of the X-band 4-bit($22.5^{\circ}$, $45^{\circ}$, $90^{\circ}$, $180^{\circ}$ BIT) diode phase shifter in the parallel plate waveguide are introduced. The simulated results of $11.25^{\circ}$, $22.5^{\circ}$ and $45^{\circ}$ dielectric phase shift layers using CST's MWS and Agilent's ADS are presented, and the measured results are compared with the simulated ones. The simulated phase shift errors at the center frequency are $0.6^{\circ}$, $0.7^{\circ}$, and $3.5^{\circ}$, respectively and the measured phase shift errors at the center frequency are $0.6^{\circ}$, $2^{\circ}$, and $5.5^{\circ}$, respectively. Also, the MWS simulated results of $22.5^{\circ}$ BIT and $45^{\circ}$ BIT phase shifter are presented and compared with the ADS simulated ones to verify the validity of the presented design concept and implementation method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.14-24
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• 2009

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.731-734
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• 1998

A scalable parallel algorithm is proposed for efficient image component labeling with local operatos on a mesh connected SIMD computer. In contrast to the conventional parallel labeling algorithms, where a single pixel is assigned to each PE, the algorithm presented here is scalable and can assign m$\times$m pixel set to each PE according to the input image size. The assigned pixel set is converted to a single pixel that has representative value, and the amount of the required memory and processing time can be highly reduced. For N$\times$N image, if m$\times$m pixel set is assigned to each PE of P$\times$P mesh, where P=N/m, the time complexity due to the communication of each PE and the computation complexity are reduced to O(PlogP) bit operations and O(P) bit operations, respectively, which is 1/m of each of the conventional method. This method also diminishes the amount of memory in each PE to O(P), and can decrease the number of PE to O(P2) =Θ(N2/m2) as compared to O(N2) of conventional method. Because the proposed parallel labeling algorithm is scalable, we can adapt to the increase of image size without the hardware change of the given mesh connected SIMD computer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.1101-1107
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• 2004

This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1219-1224
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• 1999

This paper derived Montgomery's parallel algorithms for modular multiplication based on Walter's and Iwamura's method, and compared data dependence graph of each parallel algorithm. Comparing the result, Walter's parallel algorithm has small computational index in data dependence graph, so it is selected and used to computed spatial and temporal pipelining diagrams with each projection direction for designing expansible bit-level systolic array. We also evaluated internal operation of proposed expansible systolic array C++ language.

• Journal of Korea Society of Digital Industry and Information Management
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• v.7 no.2
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• pp.59-65
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• 2011

All-optical signal processing is expected to offer advantages in speed and power consumption against over electronics signal processing. It has a potential to solve the bottleneck issues of ultra-high speed communication network nodes. All-optical serial-to-parallel and parallel-to-serial data converters would make it possible to easily process the serial data information of a high-speed optical packet without optical-to-electronic-to-optical data conversion. In this paper, we explain the principle of simple and easily expandable all-optical serial-to-parallel and parallel-to-serial data converters based on Mach-Zehnder interferometers. We experimentally demonstrate these data converters at 10Gbit/s serial data rate. They are useful all-optical devices for the all-optical implementations of label decoding, self-routing, control of variable packets, bit-wise logical operation, and data format conversion.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.17-25
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• 1999

This paper proposes a new bit-serial multiplier/divider architecture to reduce the hardware complexity significantly and to maintain the same number of cycles compared with existing architectures. Since the proposed bit-serial multiplier/divider architecture does not extend the number of bits in registers and an adde $r_tractor to calculate a partial product or a partial remainder, the hardware overhead can be greatly reduced. In addition, the proposed architecture can perform an additio $n_traction and a shift operation in parallel and the number of cycles for $\textit{N}$-bit multiplication and division for the proposed circuits is $\textit{N}$ and $\textit{N}$ + 2, repectively. Thus, the number of cycles for multiplication and division is the same compared with existing architectures. The SliM Image Processor employs the proposed multiplier/divider architecture and proves the performance of the proposed architecture.cture.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1029-1032
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• 1998

In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG $0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.477-483
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• 2015

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.