• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.819-826
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• 2018

The generalized Hamming weight is one of the important parameters of the linear code. It determines the performance of the code when the linear codes are applied to a cryptographic system. In addition, when the block code is decoded by soft decision using the lattice diagram, it becomes a measure for evaluating the state complexity required for the implementation. In particular, a bit-parallel multiplier on finite fields based on trinomials have been studied. Cellular automata(CA) has superior randomness over LFSR due to its ability to update its state simultaneously by local interaction. In this paper, we deal with the efficient synthesis of the pseudo random number generator, which is one of the important factors in the design of effective cryptosystem. We analyze the property of the characteristic polynomial of the simple 90/150 transition rule block, and propose a synthesis algorithm of the reversible 90/150 CA corresponding to the trinomials $x^2^n+x^{2^n-1}+1$($n{\geq}2$) and the 90/150 reversible CA(RCA) corresponding to the maximum weight polynomial with $2^n$ degree by using this rule block.

• Korean Journal of Optics and Photonics
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• v.29 no.1
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• pp.19-27
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• 2018

A change in object distance would generally change the magnification of an optical system. In this paper, we have proposed and designed a double-Gauss optical system with a fixed magnification and image surface regardless of any change in object distance, according to moving the lens groups a little bit to the front and rear of the stop, independently parallel to the direction of the optical axis. By maintaining a constant size of image formation in spite of various object-distance changes in a projection system such as a head-up display (HUD) or head-mounted display (HMD), we can prevent the field of view from changing while focusing in an HUD or HMD. Also, to check precisely the state of the wiring that connects semiconductor chips and IC circuit boards, we can keep the magnification of the optical system constant, even when the object distance changes due to vertical movement along the optical axis of a testing device. Additionally, if we use this double-Gauss optical system as a vision system in the testing process of lots of electronic boards in a manufacturing system, since we can systematically eliminate additional image processing for visual enhancement of image quality, we can dramatically reduce the testing time for a fast test process. Also, the Gaussian bracket method was used to find the moving distance of each group, to achieve the desired specifications and fix magnification and image surface simultaneously. After the initial design, the optimization of the optical system was performed using the Synopsys optical design software.

• Journal of IKEEE
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• v.25 no.4
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• pp.625-633
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• 2021

This paper describes a scalable architecture for flexible hardware implementation of Montgomery modular multiplication. Our scalable modular multiplier architecture, which is based on a one-dimensional array of processing elements (PEs), performs word parallel operation and allows us to adjust computational performance and hardware complexity depending on the number of PEs used, N_PE. Based on the proposed architecture, we designed a scalable Montgomery modular multiplier (sMM) core supporting eight field sizes defined in SEC2. Synthesized with 180-nm CMOS cell library, our sMM core was implemented with 38,317 gate equivalents (GEs) and 139,390 GEs for N_PE=1 and N_PE=8, respectively. When operating with a 100 MHz clock, it was evaluated that 256-bit modular multiplications of 0.57 million times/sec for N_PE=1 and 3.5 million times/sec for N_PE=8 can be computed. Our sMM core has the advantage of enabling an optimized implementation by determining the number of PEs to be used in consideration of computational performance and hardware resources required in application fields, and it can be used as an IP (intellectual property) in scalable hardware design of elliptic curve cryptography (ECC).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.9
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• pp.535-547
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• 2014

We investigate BER (Bit Error Ratio) performance according to the gain of spatial and frequency diversities in uplink SC-FDMA of SIMO (Single Input Multiple Output) systems. The main results of the analysis in this paper are as follows. First, we prove that performance of integrated system for considering spatial and frequency diversity combining in parallel is equivalent with the performance of sequential system for performing diversity combining in sequence. By signal modeling, it is demonstrated that the performances of both systems are the same when the frequency diversity combining technique of the sequential system is equal to diversity combining technique of the integrated system, and spatial diversity combining technique of the sequential system is performed as MRC in advance of frequency diversity combining. Secondly, it is found that effect on the BER performance is different according to the gain of spatial and frequency diversities, respectively. The frequency diversity gain increases by increasing the number of subcarrier. It might affect the performance improvement of high SNR(Signal to Noise Ratio) while it maintains gap between performances of ZF(Zero Forcing) and MMSE(Minimum Mean Square Error) in frequency diversity combining schemes. Also, spatial diversity gain increases as the number of receiving antennas increases. It means that it can reduce performance gap between ZF and MMSE in frequency diversity combining schemes by increasing the number of receiving antennas. In addition, it might affect the performance improvement of the whole SNR. Finally, through the analysis of performance according to the spatial diversity gain, the performance of ZF in frequency diversity combining is equal to the MMSE if the number of receiving antennas is 6 or more.

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.83-94
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• 2006

This paper describes ATM cell encipherment method using Rijndael Algorithm adopted as an AES(Advanced Encryption Standard) by NIST in 2001. ISO 9160 describes the requirement of physical layer data processing in encryption/decryption. For the description of ATM cell encipherment method, we implemented ATM data encipherment equipment which satisfies the requirements of ISO 9160, and verified the encipherment/decipherment processing at ATM STM-1 rate(155.52Mbps). The DES algorithm can process data in the block size of 64 bits and its key length is 64 bits, but the Rijndael algorithm can process data in the block size of 128 bits and the key length of 128, 192, or 256 bits selectively. So it is more flexible in high bit rate data processing and stronger in encription strength than DES. For tile real time encryption of high bit rate data stream. Rijndael algorithm was implemented in FPGA in this experiment. The boundary of serial UNI cell was detected by the CRC method, and in the case of user data cell the payload of 48 octets (384 bits) is converted in parallel and transferred to 3 Rijndael encipherment module in the block size of 128 bits individually. After completion of encryption, the header stored in buffer is attached to the enciphered payload and retransmitted in the format of cell. At the receiving end, the boundary of ceil is detected by the CRC method and the payload type is decided. n the payload type is the user data cell, the payload of the cell is transferred to the 3-Rijndael decryption module in the block sire of 128 bits for decryption of data. And in the case of maintenance cell, the payload is extracted without decryption processing.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.5
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• pp.50-60
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• 2010

For the last half a century, the personal computer and software industries have been prosperous due to the incessant evolution of computer systems. In the 21st century, the embedded system market has greatly increased as the market shifted to the mobile gadget field. While a lot of multimedia gadgets such as mobile phone, navigation system, PMP, etc. are pouring into the market, most industrial control systems still rely on 8-bit micro-controllers and simple application software techniques. Unfortunately, the technological barrier which requires additional investment and higher quality manpower to overcome, and the business risks which come from the uncertainty of the market growth and the competitiveness of the resulting products have prevented the companies in the industry from taking advantage of such fancy technologies. However, high performance, low-power and low-cost hardware and software platforms will enable their high-technology products to be developed and recognized by potential clients in the future. This paper presents such a platform for industrial embedded systems. The platform was designed based on Telechips TCC8300 multimedia processor which embedded a variety of parallel hardware for the implementation of multimedia functions. And open-source Embedded Linux, TinyX and GTK+ are used for implementation of GUI to minimize technology costs. In order to estimate the expected performance and power consumption, the performance improvement and the power consumption due to each of enabled hardware sub-systems including YUV2RGB frame converter are measured. An analytic model was devised to check the feasibility of a new application and trade off its performance and power consumption. The validity of the model has been confirmed by implementing a real target system. The cost can be further mitigated by using the hardware parts which are being used for mass production products mostly in the cell-phone market.