• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.283-289
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• 2005

In this paper, we propose two efficient symbol detection algorithms for space-frequency OFDM (SF-OFDM) transmit diversity scheme. When the number of sub-carriers in SF-OFBM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithms eliminate this interference in a parallel or sequential manlier and achieve a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithms is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithms achieve the gain improvement of about 3 dB. The symbol detectors with the proposed algorithms are designed in a hardware description language and synthesized to gate-level circuits with the $0.18{\mu}m$ 1.8V CMOS standard cell library. With the division-free architecture, the proposed SF-OFDM-PIC and SF-OFDM-SIC symbol detectors can be implemented using 140k and 129k logic gates, respectively.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.10
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• pp.2601-2619
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• 2012

A differencing multiuser detection (MUD) method is proposed for multiple-input multiple-output (MIMO) direct sequence (DS) ultra-wideband (UWB) system to cope with the multiple access interference (MAI) and the computational efficiency in Nakagami fading channel. The method, which combines a multiuser-interference-cancellation-based decision feedback equalizer using error feedback filter (MIC DFE-EFF), a coefficient optimization algorithm (COA) and a differencing algorithm (DA), is termed as MIC DFE-EFF (COA) with DA for short. In the paper, the proposed MUD method is illuminated from the rudimental MIC DFE-EFF to the advanced MIC DFE-EFF (COA) with DA step by step. Firstly, the MIC DFE-EFF system performance is analyzed by minimum mean square error criterion. Secondly, the COA is investigated for optimization of each filter coefficient. Finally, the DA is introduced to reduce the computational complexity while sacrificing little performance. Simulations show a significant performance gain can be achieved by using the MIC DFE-EFF (COA) with DA detector. The proposed MIC DFE-EFF (COA) with DA improves both bit error rate performance and computational efficiency relative to DFE, DFE-EFF, parallel interference cancellation (PIC), MIC DFE-EFF and MIC DFE-EFF with DA, though it sacrifices little system performance, compared with MIC DFE-EFF (COA) without DA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.115-124
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• 2004

This paper proposes a high efficient and low power FIR filter chip for partial-response maximum likelihood (PRML) disk drive read channels; it is a 6-bit, 8-tap digital FIR filter. The proposed filter employs a parallel processing architecture and consists of 4 pipeline stages. It uses the modified Booth algorithm for multiplication and compressor logic for addition. CMOS pass-transistor logic is used for low power consumption and single-rail logic is used to reduce the chip area. The proposed filter is actually implemented and the chip dissipates 120mV at 100MHz, uses a 3.3V power supply and occupies 1.88 ${\times}$ 1.38 $\textrm{mm}^2$. The implemented filter requires approximately 11.7% less power compared with the existing architectures that use the similar technology.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.7
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• pp.411-421
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• 2002

In this Paper we propose a new Image analysis algorithm for microarray processing and a method to locate the position of the grid cell using the topology of the grid spots. Microarray is a device which enables a parallel experiment of 10 to 100 thousands of test genes in order to measure the gene expression. Because of the huge data obtained by a experiment automated image analysis is needed. The final output of this microarray experiment is a set of 16-bit gray level image files which consist of grid-structured spots. In this paper we propose one algorithm which located the address of spots (spot indices) using graph structure from image data and a method which determines the precise location and shape of each spot by measuring the inclination of grid structure. Several experiments are given from real data sets.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.121-126
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• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.11
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• pp.117-126
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• 2003

GA(genetic algorithm) has a powerful searching ability and is comparatively easy to use and to apply as well. By that reason, GA is in the spotlight these days as an optimization skill for mechanical systems.$^1$However, GA has a low efficiency caused by a huge amount of repetitive computation and an inefficiency that GA meanders near the optimum. It also can be shown a phenomenon such as genetic drifting which converges to a wrong solution.$^{8}$ These defects are the reasons why GA is not widdy applied to real world problems. However, the low efficiency problem and the meandering problem of GA can be overcomed by introducing parallel computation$^{7}$ and gray code$^4$, respectively. Standard GA(SGA)$^{9}$ works fine on small to medium scale problems. However, SGA done not work well for large-scale problems. Large-scale problems with more than 500-bit of sere's have never been tested and published in papers. In the result of using the SGA, the powerful searching ability of SGA doesn't have no effect on optimizing the problem that has 96 design valuables and 1536 bits of gene's length. So it converges to a solution which is not considered as a global optimum. Therefore, this study proposes ExpGA(experience GA) which is a new genetic algorithm made by applying a new probability parameter called by the experience value. Furthermore, this study finds the solution throughout the whole field searching, with applying ExpGA which is a optimization technique for the structure having genetic drifting by the standard GA and not making a optimization close to the best fitted value. In addition to them, this study also makes a research about the possibility of GA as a optimization technique of large-scale design variable problems.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.4
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• pp.753-758
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• 2009

Recently the high-end CMOS image sensors are developed, conforming to the SMIA CCP2 specification, which is a high-speed low-power serial interface based on LVDS technology. But this kind of technology trend makes the existing equipments are no longer useful, although their capability is still good enough to handle the recent image sensors if there was no interfacing problem. In this paper, we propose and realize a data protocol conversion system that translates the SMIA CCP2 serial signals into the existing 10-bit parallel signals. The proposed system is composed of a de-serializer and a FPCA chip, and thus can be constructed on a small PCB which enables easy integration between the existing equipments and the new high-end image sensors. Besides, the maximum transfer rate by the SMIA specification is also achieved on the implemented system. So it is expected that the implemented system can be used as a general-purpose protocol converter in a variety of sensor-related application fields.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2143-2149
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• 2012

DVB-S2 employs LDPC codes which approach to the Shannon's limit, since it has characteristics of a good distance, error floor does not appear. Furthermore it is possible to processes full parallel processing. However, it is very difficult to high speed decoding because of a large block size and number of many iterations. This paper present HSS algorithm to reduce the iteration numbers without performance degradation. In the flooding scheme, the decoder waits until all the check-to-variable messages are updated at all parity check nodes before computing the variable metric and updating the variable-to-check messages. The HSS algorithm is to update the variable metric on a check by check basis in the same way as one code draws benefit from the other. Eventually, LDPC decoding speed based on HSS algorithm improved 30% ~50% compared to conventional one without performance degradation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.3
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• pp.47-61
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• 2012

parallel transmitting system with channel bonding method have been proposed to transmit mass content such as UHD(Ultra High Definition) in HFC(Hybrid Fiber Coaxial) networks. However, this system may lead to channel resource problem because the system needs many channels to transmit mass content. In this paper, we analyze three effective bandwidth approximation algorithms to use the bonding channel efficiently. These algorithms are the effective bandwidth of Gaussian approximation method algorithm proposed by Guerin, the effective bandwidth based on statistics of video frames proposed by Lee and the effective bandwidth based on Gaussian traffic proposed by Nagarajan. We also evaluate compatibility of algorithms to the mass broadcasting service. OPNET simulator is used to evaluate the performance of the algorithms. For accuracy of simulation, we make mass source from real HD broadcasting stream.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.167-173
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• 2015

This paper presents a study on the Full-HD HEVC(High Efficiency Video Coding) encoder IP(Intellectual Property) design. The designed IP is for HEVC main profile 4.1, and performs encoding with a speed of 60 fps of full high definition. Before hardware and software design, overall reference model was developed with C language, and we proposed a parallel processing architecture for low-power consumption. And also we coded firmware and driver programs relating IP. The platform for verification of developed IP was developed, and we verified function and performance for various pictures under several encoding conditions by implementing designed IP to FPGA board. Compared to HM-13.0, about 35% decrease in bit-rate under same PSNR was achieved, and about 25% decrease in power consumption under low-power mode was performed.