• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.1
• /
• pp.51-59
• /
• 2004

We design multilevel coding(MLC) with a semi bit-interleaved coded modulation(BICM) scheme based on low density parity check(LDPC) codes. Different from traditional designs, we joint the MLC and BICM together by using the Gray mapping, which can transmit the multimedia data over several equivalent channels with different code rates. To get a good performance from signal-to-noise ratio(SNR) very close to the capacity of the additive white Gaussian noise(AWGN) channel, random regular LDPC code and a simple semi-algebra LDPC(SA-LDPC) code are discussed in MLC with parallel independent decoding(PID). Finally, the numerical results demonstrate that the proposed scheme could achieve both power and bandwidth efficiency for multimedia communication system.

• ETRI Journal
• /
• v.46 no.3
• /
• pp.485-500
• /
• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.29 no.5
• /
• pp.336-343
• /
• 2018

We herein present the design and fabrication of a Rx core chip operating in the X-band (10.5~13 GHz) using Win's commercial $0.25-{\mu}m$ GaAs pHEMT process technology. The X-band core chip comprises a low-noise amplifier, a four-bit phase shifter, and a serial-to-parallel data converter. The size is $1.75mm{\times}1.75mm$, which is the state-of-the-art size. The gain and noise figure are more than 10 dB but less than 2 dB, and both the input and output return losses are less than 10 dB. The RMS phase error is less than $5^{\circ}$, and the P1dB is 2 dBm at 12.5 GHz, the performance of which is equivalent to other GaAs core chips. The fabricated core chip was packaged in a QFN package type with a size of $3mm{\times}3mm$ for the convenience of assembly. We confirmed that the performance of the packaged core chip was almost the same as that of the chip itself.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.11
• /
• pp.24-32
• /
• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Korean Journal of Applied Biomechanics
• /
• v.15 no.4
• /
• pp.43-53
• /
• 2005

This study is to define how the difference of athletic change influence on the last regrasp after somersault in Belle movement of parallel bars. For his study, the following conclusion was produced by analysis of athletic change by means of three dimensional visual image in three athlete of nation. 1. As the picture of S1, there are total used time(2.01 sec), S3(2.17 sec) and S2(2.19 sec). In case of a short needed time, it is difficult for them to perform the remaining movement of the vertical elevating flight easily and comfortably, it is judged as performing the small movement with restrict swing. 2 In the change of body center sped by each event, it is calculated as $-89.1^{\circ}$ the narrowest in S1, $-81.96^{\circ}$ the widest and then $86.34^{\circ}$ in S3. In E3 event, average compound speed is 4.07m/s, S2 showed the fastest speed of 4.14m/s whereas S1 the narrowest angle of 3.95m/s. 3. A shoulder joint and coxa are the period of mention in E3. In E4 which was pointed out the longest vertical distance, S2 that is indicated the highest vertical height as the period of detach in parallel bars. showed -3.91m. This is regarded as a preparatory movement for dynamic performance after using effectively elastic movement of shoulder joint and coxa while easily going up with turning back movement. In the 5th phrase, long airborne time and vertical change position is showed as the start while regrasping securely air flight movement from high position. 4. In E5, a long flight time and a long vertical displacement were shown as the regrasp after somersault efficiently in high position with stability from the point of the highest peak of the center of the body. Especially, S2 is marked as a little bit long position, while S1 is reversely indicated as performing somersault and unstable motion in a low position. 5. In E3, at the point of the largest extension of the shoulder joint and hip joint the shoulder joint is largely marked in $182^{\circ}$ and the hip point $182^{\circ}$ in S2. The shoulder joint is marked at the smallest angle in $177^{\circ}$ and the hip point $176^{\circ}$ in S1. And S1 is being judged by its performance of the less self - confident motion with lessening a breath of swing. S2 makes the most use of flexion and extension of the shoulder joint and the hip joint effectively. It was performed greatly with swinging and dropping the rotary movement and the rotary inertia naturally. 6. In E6, as the point of regrasp of the upper arm in parallel bars it is recognized by the that of components of vertical and horizontal velocity stably. During this study, the insufficient thing and the study on the parallel bars at a real game later are more activated than now. If it is really used as the basic materials by means of Belle Picked Study of Super E level after Bell movement, you may perceive the technique movement previously and perform without difficulty. Especially, such technique as crucifix is quite advantageous for oriental people thanks to small body shape condition. In conclusion we will nicely prepare for our suitable environment to gradually lessen trials and errors by analyzing and studying kinematically this movement.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.11 no.3
• /
• pp.23-32
• /
• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.13 no.1
• /
• pp.47-57
• /
• 2003

In this paper, we firstly evaluate the resistance of the reduced 5-round version of the block cipher CIKS-1 against linear cryptanalysis(LC) and show that we can attack full-round CIKS-1 with \ulcorner56-bit key through the canonical extension of our attack. A feature of the CIKS-1 is the use of both Data-Dependent permutations(DDP) and internal key scheduling which consist in data dependent transformation of the round subkeys. Taking into accout the structure of CIKS-1 we investigate linear approximation. That is, we consider 16 linear approximations with p=3/4 for 16 parallel modulo $2^2$ additions to construct one-round linear approximation and derive one-round linear approximation with the probability P=1/2+$2^{-17}$ by Piling-up lemma. Then we present 3-round linear approximation with 1/2+$2^{-17}$ using this one-round approximation and attack the reduced 5-round CIKS-1 with 64-bit block by LC. In conclusion we present that our attack requires $2^{38}$chosen plaintexts with a probability of success of 99.9% and about $2^{67-7}$encryption times to recover the last round key.(But, for the full-round CIKS-1, our attack requires about $2^{166}$encryption times)

• Journal of Sensor Science and Technology
• /
• v.14 no.1
• /
• pp.33-41
• /
• 2005

For more convenient electrode-electrolyte interface impedance analysis in biosensor, a stand-alone impedance measurement system is required. In our study, we developed a PC-based portable system to analyze impedance of the electrochemical cell using microprocessor. The devised system consists of signal generator, programmable amplifiers, A/D converter, low pass filter, potentiostat, I/V converter, microprocessor, and PC interface. As a microprocessor, PIC16F877 which has the processing speed of 5 MIPS was used. For data acquisition, the sampling rate at 40 k samples/sec, resolution of 12 bit is used. RS-232 with 115.2 kbps speed is used for the PC communication. The square wave was used as stimuli signal for impedance analysis and voltage-controlled current measurement method of three-electrode-method were adopted. Acquired voltage and current data are calculated to multifrequency impedance signal after Fourier transform. To evaluate the implemented system, we set up the dummy cell as equivalent circuit of which was composed of resistor, parallel circuit of capacitor and resistor connected in parallel and measured the impedance of the dummy cell; the result showed that there exist accuracy within 5 % errors and reproduction within 1 % errors compared to output of Hioki LCR tester and HP impedance analyzer as a standard product. These results imply that it is possible to analyze electrode-electrolyte interface impedance quantitatively in biosensor and to implement the more portable high speed impedance analysis system compared to existing systems.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.19-24
• /
• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.8A
• /
• pp.1198-1205
• /
• 2000

In this paper, we introduce a modified interference cancellation scheme to overcome MAI in DS-CDMA. Among ICs(Interference Cancellers), PIC(Parallel IC) requires the more complexity, and SIC(Successive IC) faces the problems of the long delay time. Most of all, the adaptive detector achieves the good BER performance using the adaptive Inter conducted iteration algorithm. So it requires many iterations. To resolve the problems of them, we propose an improved adaptive detector that the received signal removed MAI through the sorting scheme and the cancellation method are fed into the adaptive filter. Because the improved input signal is fed into the adaptive filter, it has the same BER performance only using smaller iterations than the conventional adaptive detector, and the proposed detector having adaptive filter requires less complexity than the other detectors.