• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1537-1545
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• 1993

In this paper, we design a pattern generator and a fault position detector to implement the proposed fault test algorithms which are Column Weight Sensitive Fault (CWSF) test algorithm and bit line decoder fault test algorithm for performing the Built-In Self Test(BIST) in RAM. A pattern generator consists of an address generator and a data generator. An address generator is divided into a row address generator for effective address and a column address generator for sequential and parallel addresses. A fault position detector is designed to determine whether full occurred or not and to find the position of the fault. We verify the implemented circuits by the simulation.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.309-313
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• 2009

In this paper, the network performance of a turbo coded optical code division multiple access (CDMA) system with cross-layer, which is between physical and network layers, concept is analyzed and simulated. We consider physical and MAC layers in a cross-layer concept. An intensity-modulated/direct-detection (IM/DD) optical system employing pulse position modulation (PPM) for satellite broadcasting communications is considered. In order to increase the system performance, turbo codes composed of parallel concatenated convolutional codes (PCCCs) is utilized. The network performance is evaluated in terms of bit error probability (BEP). From the simulation results, it is demonstrated that turbo coding offers considerable coding gain with reasonable encoding and decoding complexity. Also, it is confirmed that the performance of such an optical CDMA network can be substantially improved by increasing the interleaver length and the number of iterations in the decoding process. The results of this paper can be applied to implement the satellite broadcasting communications.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.314-319
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• 2009

In this paper, the network performance of a turbo coded optical code division multiple access (COMA) system with cross-layer, which is between physical and network layers, concept is analyzed and simulated We consider physical and MAC layers in a cross-layer concept. An intensity-modulated/direct-detection (IM/DD) optical system employing pulse position modulation (PPM) is considered In order to increase the system performance, turbo codes composed of parallel concatenated convolutional codes (PCCCs) is utilized. The network performance is evaluated in terms of bit error probability (BEP). From the simulation results, it is demonstrated that turbo coding offers considerable coding gain with reasonable encoding and decoding complexity. Also, it is confirmed that the performance of such an optical COMA network can be substantially improved by increasing the interleaver length and the number of iterations in the decoding process. The results of this paper can be applied to implement the indoor optical wireless LANs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1245-1251
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• 1999

A 1.25Gb/s path control switch chip has been designed and implemented with COMPASS tool and 0.8${\mu}{\textrm}{m}$ CMOS gate-array of LG semiconductor. This device controls the path of digital singnals in SDH-based transmission system. The proposed switch chip is suitable for self-healing operations both in a linear network and an unidirectonal ring, The self-healing operation of the switch is effectively done by the configuration information stored in the resisters of the switch. The test device adapted to SDH-based transmission system, show immediate restoration and a 10-11~10-12 bit error raito. And 2.5Gb/s or more high throughput can be realized by combining rwo identical or more switches with the parallel architecture.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.11
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• pp.90-100
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• 1997

In this paper, we propose a new optical thresold generator as a key-stream genrator for stream cipher systems. The random key-bit stream is generated by a digital generator that is composed of LFSRs and nonlinear ligics. Digital implementatin of a key-stream generator requires large memory to implement programmable tapping points. This memory problem may be overcome easily by using the proposed optical system which has the proberty of 2D parallel processing.To implement hte threshold generator optically, we use conventional twisted nematic type SLMs (LCDs). This proposed system is based on the shadow casting technique for the AND operation between taps and sregister stages. It is also based on the proposed PMRS method for modulo 2 addition. The proposed PMRS method uses the property of light's polarization on LCD and can be implemented optically using one LCD and some mirrors. One of the major advantages of the proosed system is that there is no limitation of the number of the progarmmable tapping points. Therefore, the proposed system can be applied for the 2D encryption system which processes large amounts of data such as 2D images. We verify the proposed system with some simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1022-1032
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• 2002

A multibit DRAM BIST methodology reducing redundancy programming overhead has been proposed. It is capable of counting and locating faulty bits simultaneously with the test. If DRAM cells are composed of n blocks generally, the proposed BIST can detect the state of no error, the location of faulty bit block if there is one error and the existence of errors in more than two blocks, which are n + 2 states totally, with only n comparators and an 3 state encoder. Based on the proposed BIST methodology, the testing scheme which can detect the number and locations of faulty bits with the errors in two or more blocks, can be easily implemented. Based on performance evaluation, the test and redundancy programming time of 64MEG DRAM with 8 blocks is reduced by 1/750 times with 0.115% circuit overhead.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.2
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• pp.95-101
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• 2014

In this paper, UPS, with a built-in instantaneous sag drop compensation features, was developed to improve performance. The improved UPS, using instantaneous moving average method, compensates by quickly measuring the voltage and series inverter of half-bridge type, using line-interactive method that links with the voltage of the battery and power source, was developed. In addition, by developing a parallel inverter that uses a high-efficiency PWM switching method, overall UPS system was enhanced. To verify the performance of the proposed algorithm, single-phase 5[kVA] UPS systems were designed and the experimental system was constructed. The low-cost type of Cortex-M3 module CPU STM32F103R8T6 (32[bit]) is attached and the switching time of mode transfer was set within 4 [ms]. THD of the linear load operates in less than 3[%], and the stability of the output voltage operates in approximately ${\pm}2[%]$ range. The superior performance of the operations was confirmed with the system set as above.

• Journal of Korea Game Society
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• v.14 no.6
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• pp.59-68
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• 2014

Memory bandwidth requirements of UHD (Ultra High Definition $4096{\times}2160$) game scenes have been much more increasing. This paper presents a lossless DPCM-GR based compression algorithm using CUDA for solving the memory bandwidth problem without sacrificing image quality, which is modified from DDPCM-GR [4] to support bit parallel pipelining. The memory bandwidth efficiency increases because of using the shared memory of CUDA. Various asynchronous transfer configurations which can overlap the kernel execution and data transfer between host and CUDA are implemented with the page-locked host memory. Experimental results show that the maximum 31.3 speedup is obtained according to CPU time. The maximum 30.3% decreases in the computation time among various configurations.

• Journal of the Korean Society of Propulsion Engineers
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• v.12 no.1
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• pp.1-6
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• 2008

Performance test of the 30-ton class liquid rocket engine turbopump turbine has been conducted using high pressure cold air. Overall performance of the two kinds of turbine rotors - rotor with knife-edged L.E blades and with rounded L.E blades - has been measured for various rotational speed and turbine pressure ratio. The effect of rotational speed and turbine pressure ratio on the turbine axial force behavior also has been measured in parallel. Test results have revealed that the efficiency of knife edged L.E. turbine is a little bit higher than that of rounded L.E. turbine. The axial force of the turbine varied linearly with respect to rotational speed and its magnitude largely depended on turbine pressure ratio.